H55S5122DFR-75M datasheet, PDF

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H55S5122DFR-75M: DescriptionSynchronous DRAM, 16MX32, 6ns, CMOS, PBGA90; Categorystorage storage; File Size841KB，54 Pages; ManufacturerSK Hynix; Websitehttp://www.hynix.com/eng/; Environmental Compliance

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H55S5122DFR-75M Overview

Synchronous DRAM, 16MX32, 6ns, CMOS, PBGA90

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512MBit MOBILE SDR SDRAMs based on 4M x 4Bank x32 I/O

Specification of

512M (16Mx32bit) Mobile SDRAM

Memory Cell Array

- Organized as 4banks of 4,194,304 x32

This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for

use of circuits described. No patent licenses are implied.

Rev 1.5 / Jan. 2009

512Mbit (16Mx32bit) Mobile SDR Memory

H55S5122DFR Series / H55S5132DFR Series

DESCRIPTION

The Hynix H55S5122DFR is suited for non-PC application which use the batteries such as PDAs, 2.5G and 3G cellular

phones with internet access and multimedia capabilities, mini-notebook, hand-held PCs.

The Hynix 512M Mobile SDRAM is 536,870,912-bit CMOS Mobile Synchronous DRAM(Mobile SDR), ideally suited for the

main memory applications which requires large memory density and high bandwidth. It is organized as 4banks of

4,194,304x32.

Mobile SDRAM is a type of DRAM which operates in synchronization with input clock. The Hynix Mobile SDRAM latch

each control signal at the rising edge of a basic input clock (CLK) and input/output data in synchronization with the

input clock (CLK). The address lines are multiplexed with the Data Input/ Output signals on a multiplexed x32 Input/

Output bus. All the commands are latched in synchronization with the rising edge of CLK.

The Mobile SDRAMs provides for programmable read or write Burst length of Programmable burst lengths: 1, 2, 4, 8

locations or full page. An AUTO PRECHARGE function may be enabled to provide a self-timed row precharge that is ini-

tiated at the end of the burst access. The Mobile SDRAM uses an internal pipelined architecture to achieve high-speed

operation. This architecture is compatible with the

rule of prefetch architectures, but it also allows the column

address to be changed on every clock cycle to achieve a high-speed, fully random access. Precharging one bank while

accessing one of the other three banks will hide the precharge cycles and provide seamless, high-speed, random-

access operation.

Read and write accesses to the Hynix Mobile SDRAMs are burst oriented;

accesses start at a selected location and continue for a programmed number of locations in a programmed sequence.

Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command.

The address bits registered coincident with the ACTIVE command are used to select the bank and the row to be

accessed. The address bits registered coincident with the READ or WRITE command are used to select the bank and

the starting column location for the burst access. A burst of Read or Write cycles in progress can be terminated by a

burst terminate command or can be interrupted and replaced by a new burst Read or Write command on any

cycle(This pipelined design is not restricted by a

rule).

The Hynix Mobile SDR also provides for special programmable options including Partial Array Self Refresh of full array,

half array, quarter array Temperature Compensated Self Refresh of 45 or 85 degrees

The Hynix Mobile SDR has the special Low Power function of Auto TCSR(Temperature Compensated Self Refresh) to

reduce self refresh current consumption. Since an internal temperature sensor is implanted, it enables to automatically

adjust refresh rate according to temperature without external EMRS command.

Deep Power Down Mode is a additional operating mode for Mobile SDR. This mode can achieve maximum power

reduction by removing power to the memory array within each Mobile SDR. By using this feature, the system can cut

off almost all DRAM power without adding the cost of a power switch and giving up mother-board power-line layout

flexibility.

All inputs are LV-CMOS compatible. Devices will have a V

and V

DDQ

supply of 1.8V (nominal).

Rev 1.5 / Jan. 2009

H55S5122DFR-75M Related Products

	H55S5122DFR-75M	H55S5122DFR-60M	H55S5122DFR-A3M	H55S5132DFR-60M	H55S5132DFR-75M	H55S5132DFR-A3M
Description	Synchronous DRAM, 16MX32, 6ns, CMOS, PBGA90	512MBit MOBILE SDR SDRAMs based on 4M x 4Bank x32 I/O	Synchronous DRAM, 16MX32, 7ns, CMOS, PBGA90	Synchronous DRAM, 16MX32, 5.4ns, CMOS, PBGA90	512MBit MOBILE SDR SDRAMs based on 4M x 4Bank x32 I/O	Synchronous DRAM, 16MX32, 7ns, CMOS, PBGA90

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