HY5DV651622TC-75 datasheet, PDF

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HY5DV651622TC-75: DescriptionDDR DRAM, 4MX16, CMOS, PDSO66, 0.400 X 0.875 INCH, 0.65 MM PITCH, TSOP2-66; Categorystorage storage; File Size78KB，9 Pages; ManufacturerSK Hynix; Websitehttp://www.hynix.com/eng/

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HY5DV651622TC-75 Overview

DDR DRAM, 4MX16, CMOS, PDSO66, 0.400 X 0.875 INCH, 0.65 MM PITCH, TSOP2-66

HY5DV651622TC-75 Parametric

Parameter Name	Attribute value
Maker	SK Hynix
Parts packaging code	TSOP2
package instruction	TSOP2,
Contacts	66
Reach Compliance Code	unknown
ECCN code	EAR99
access mode	FOUR BANK PAGE BURST
JESD-30 code	R-PDSO-G66
JESD-609 code	e6
length	22.225 mm
memory density	67108864 bit
Memory IC Type	DDR DRAM
memory width	16
Number of functions	1
Number of ports	1
Number of terminals	66
word count	4194304 words
character code	4000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	4MX16
Package body material	PLASTIC/EPOXY
encapsulated code	TSOP2
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE
Certification status	Not Qualified
Maximum seat height	1.2 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3.15 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	TIN BISMUTH
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	DUAL
width	10.16 mm

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HY5DV651622

4 Banks x 1M x 16Bit DOUBLE DATA RATE SDRAM

PRELIMINARY

DESCRIPTION

The Hyundai HY5DV651622 is a 67,108,864-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited

for the point to point applications which require high bandwidth. HY5DV651622 is organized as 4 banks of

1,048,576x16.

HY5DV651622 offers fully synchronous operations referenced to both rising and falling edges of the clock. While all

addresses and control inputs are latched on the rising edges of the clock(falling edges of the CLK), Data(DQ), Data

strobes(LDQS/UDQS) and Write data masks(LDM/UDM) inputs are sampled on both rising and falling edges of it. The

data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage

levels are compatible with SSTL_2.

Mode Register Set options include the length of pipeline (CAS latency of 2.0 / 2.5 / 3.0), the number of consecutive

read or write cycles initiated by a single control command (Burst length of 2 / 4 / 8), and the burst count

sequence(sequential or interleave). Because data rate is doubled through reading and writing at both rising and falling

edges of the clock, 2X higher data bandwidth can be achieved than that of traditional (single data rate) Synchronous

DRAM.

FEATURES

•

3.3V for V

and 2.5V for V

DDQ

power supplies

All inputs and outputs are compatible with SSTL_2

interface

JEDEC standard 400mil 66pin TSOP-II with 0.65mm

pin pitch

Fully differential clock operations(CLK & CLK)

•

All addresses and control inputs except Data, Data

strobes and Data masks latched on the rising edges

of the clock

Data(DQ), Data strobes(LDQS/UDQS) and Write

masks(LDM/UDM) latched on both rising and falling

edges of the clock

Data outputs on LDQS/UDQS edges when read

(edged DQ)

•

Write mask byte controls by LDM and UDM

Programmable CAS Latency 2.0 / 2.5 / 3.0

Programmable Burst Length 2 / 4 / 8 with both

sequential and interleave mode

Internal four bank operations with single pulsed RAS

Auto refresh and self refresh supported

4096 refresh cycles / 64ms

•

Data inputs on LDQS/UDQS centers when write

(centered DQ)

Data strobes synchronized with output data for read

and input data for write

Delay Locked Loop(DLL) installed with DLL reset

mode

•

ORDERING INFORMATION

Part No.

HY5DV651622TC-G6

HY5DV651622TC-G7

HY5DV651622TC-7

HY5DV651622TC-75

HY5DV651622TC-8

* JEDEC Defined Specifications compliant

Power Supply

Clock Frequency

166MHz

143MHz

Organization

Interface

Package

=3.3V

DDQ

=2.5V

133MHz(*PC266A)

125MHz(*PC266B)

100MHz(*PC200)

4Banks x 1Mbit x16

SSTL_2

400mil 66pin

TSOP II

This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any

responsibility for use of circuits described. No patent licenses are implied.

Rev. 0.8/ Oct.99

HY5DV651622TC-75 Related Products

	HY5DV651622TC-75	HY5DV651622TC-8	HY5DV651622TC-7
Description	DDR DRAM, 4MX16, CMOS, PDSO66, 0.400 X 0.875 INCH, 0.65 MM PITCH, TSOP2-66	DDR DRAM, 4MX16, CMOS, PDSO66, 0.400 X 0.875 INCH, 0.65 MM PITCH, TSOP2-66	DDR DRAM, 4MX16, CMOS, PDSO66, 0.400 X 0.875 INCH, 0.65 MM PITCH, TSOP2-66
Parts packaging code	TSOP2	TSOP2	TSOP2
package instruction	TSOP2,	TSOP2,	TSOP2,
Contacts	66	66	66
Reach Compliance Code	unknown	unknown	unknown
ECCN code	EAR99	EAR99	EAR99
access mode	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST
JESD-30 code	R-PDSO-G66	R-PDSO-G66	R-PDSO-G66
JESD-609 code	e6	e6	e6
length	22.225 mm	22.225 mm	22.225 mm
memory density	67108864 bit	67108864 bit	67108864 bit
Memory IC Type	DDR DRAM	DDR DRAM	DDR DRAM
memory width	16	16	16
Number of functions	1	1	1
Number of ports	1	1	1
Number of terminals	66	66	66
word count	4194304 words	4194304 words	4194304 words
character code	4000000	4000000	4000000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	70 °C	70 °C	70 °C
organize	4MX16	4MX16	4MX16
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TSOP2	TSOP2	TSOP2
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE
Certification status	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1.2 mm	1.2 mm	1.2 mm
Maximum supply voltage (Vsup)	3.6 V	3.6 V	3.6 V
Minimum supply voltage (Vsup)	3.15 V	3.15 V	3.15 V
Nominal supply voltage (Vsup)	3.3 V	3.3 V	3.3 V
surface mount	YES	YES	YES
technology	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal surface	TIN BISMUTH	TIN BISMUTH	TIN BISMUTH
Terminal form	GULL WING	GULL WING	GULL WING
Terminal pitch	0.65 mm	0.65 mm	0.65 mm
Terminal location	DUAL	DUAL	DUAL
width	10.16 mm	10.16 mm	10.16 mm
Maker	SK Hynix	-	SK Hynix

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