• 32-bit Standard Footprint supports densities from
16K x 32 through 1M x 32
• High-speed SRAMs
— Access time of 12 ns
• Low active power
— 3.3W (max.) at 12 ns
• 72 pins
• Available in ZIP, SIMM, or angled SIMM format
packages mounted on an epoxy laminate substrate. Four chip
selects are used to independently enable the four bytes. Read-
ing or writing can be executed on individual bytes or any com-
bination of multiple bytes through proper use of selects.
The CYM1851V33 is designed for use with standard 72-pin
SIMM sockets. The pinout is downward compatible with the
64-pin JEDEC ZIP/SIMM module family (CYM1821,
CYM1831, CYM1836, and CYM1841). Thus, a single mother-
board design can be used to accommodate memory depth
ranging from 16K words (CYM1821) to 1,024K words
(CYM1851). The CYM1851V33 is offered in vertical and an-
gled SIMM configurations and both are available with either
tin-lead or 10 micro-inches of gold flash on the edge contacts.
Presence detect pins (PD
0
−PD
3
) are used to identify module
memory density in applications where modules with alternate
word depths can be interchanged.
Functional Description
The CYM1851V33 is a 3.3V high-performance 32-megabit
static RAM module organized as 1,024K words by 32 bits. This
module is constructed from eight 1,024K x 4 SRAMs in SOJ
Logic Block Diagram
PD
0
-
PD
1
-
PD
2
-
PD
3
-
GND
OPEN
GND
OPEN
Pin Configuration
ZIP/SIMM
Top View
A
0
-A
19
OE
WE
1M x 4
SRAM
CS
1
1M x 4
SRAM
CS
2
1M x 4
SRAM
CS
3
1M x 4
SRAM
CS
4
I/O
24
−
I/O
27
I/O
16
−
I/O
19
I/O
8
−
I/O
11
I/O
0
−
I/O
3
20
4
1M x 4
SRAM
I/O
4
–I/O
7
4
4
1M x 4
SRAM
4
I/O
12
–I/O
15
4
1M x 4
SRAM
4
I/O
20
–I/O
23
NC
PD
3
PD
0
I/O
0
I/O
1
I/O
2
I/O
3
V
CC
A
7
A
8
A
9
I/O
4
I/O
5
I/O
6
I/O
7
WE
A
14
CS
1
CS
3
A
16
GND
I/O
16
I/O
17
I/O
18
I/O
19
A
10
A
11
A
12
A
13
I/O
20
I/O
21
I/O
22
I/O
23
GND
A
19
NC
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
NC
PD
2
GND
PD
1
I/O
8
I/O
9
I/O
10
I/O
11
A
0
A
1
A
2
I/O
12
I/O
13
I/O
14
I/O
15
GND
A
15
CS
2
CS
4
A
17
OE
I/O
24
I/O
25
I/O
26
I/O
27
A
3
A
4
A
5
V
CC
A
6
I/O
28
I/O
29
I/O
30
I/O
31
A
18
NC
4
1M x 4
SRAM
I/O
28
–I/O
31
4
Cypress Semiconductor Corporation
Document #: 38-05268 Rev. **
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised March 15, 2002
PRELIMINARY
Selection Guide
1851V33-12
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum Standby Current (mA)
Shaded area contains advance information.
CYM1851V33
1851V33-15
15
1250
520
1851V33-20
20
1100
480
1851V33-25
25
1100
480
1851V33-35
35
1100
480
12
1450
540
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. –55°C to +125°C
Ambient Temperature with
Power Applied............................................... –10°C to +85°C
Supply Voltage to Ground Potential ............... –0.5V to +4.6V
DC Voltage Applied to Outputs
in High Z State ................................................ –0.5V to +V
CC
DC Input Voltage............................................ –0.5V to +4.6V
Operating Range
Range
Commercial
Ambient
Temperature
0°C to +70°C
V
CC
3.3V
+10%/
−5%
Electrical Characteristics
Over the Operating Range
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
Output Leakage Current
V
CC
Operating Supply
Current
GND < V
I
< V
CC
GND < V
O
< V
CC
, Output Disabled
V
CC
= Max., I
OUT
= 0 mA,
CS
N
< V
IL,
f
=
f
MAX
-12
-15
-20, -25, -35
I
SB1
Automatic CS Power-Down
Current
[1]
Max. V
CC
, CS > V
IH
,
Min. Duty Cycle = 100%
-12
-15
-20, -25, -35
I
SB2
Automatic CS Power-Down
Current
[1]
Max. V
CC
, CS > V
CC
−
0.2V, V
IN
> V
CC
−
0.2V,
or V
IN
< 0.2V
Test Conditions
V
CC
= Min., I
OH
=
−4.0
mA
V
CC
= Min., I
OL
= 4.0 mA
2.0
–0.3
–16
–10
Min.
2.4
0.4
V
CC
+ 0.3
0.8
+16
+10
1450
1250
1100
540
520
480
270
Max.
Unit
V
V
V
V
µA
µA
mA
mA
mA
mA
mA
mA
mA
Shaded area contains advance information.
Capacitance
[2]
Parameter
C
INA
C
INB
C
OUT
Description
Input Capacitance (WE, OE, A
0
−
19
)
Input Capacitance (CS)
Output Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz,
V
CC
= 5.0V
Max.
40
10
8
Unit
pF
pF
pF
Notes:
1. A pull-up resistor to V
CC
on the CS input is required to keep the device deselected during V
CC
power-up, otherwise I
SB
will exceed values given.
2. Tested on a sample basis.
Document #: 38-05268 Rev. **
Page 2 of 9
PRELIMINARY
AC Test Loads and Waveforms
R1 317
Ω
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
R2
351
Ω
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
R2
351
Ω
R1 317
Ω
3.0V
90%
GND
10%
CYM1851V33
ALL INPUT PULSES
90%
10%
≥
5 ns
≥
5 ns
(a)
(b)
Equivalent to:
OUTPUT
THÉVENIN
167
Ω
EQUIVALENT
1.73V
Switching Characteristics
Over the Operating Range
[3]
1851V33-12
Parameter
READ CYCLE
t
RC
t
AA
t
OHA
t
ACS
t
DOE
t
LZOE
t
HZOE
t
LZCS
t
HZCS
t
PD
WRITE CYCLE
[6]
t
WC
t
SCS
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
Write Cycle Time
CS LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z
WE LOW to High Z
[5]
12
9
9
0
1
10
7
1
3
0
7
15
10
10
0
1
12
8
1
3
0
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CS LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
CS LOW to Low Z
[4]
CS HIGH to High Z
[4, 5]
CS HIGH to Power-Down
3
7
12
0
7
3
8
15
3
12
7
0
8
12
12
3
15
8
15
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Min.
Max.
1851V33-15
Min.
Max.
Unit
Shaded area contains advance information.
Notes:
3. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and 30-pF load capacitance.
4. At any given temperature and voltage condition, t
HZCS
is less than t
LZCS
for any given device. These parameters are guaranteed and not 100% tested.
5. t
HZCS
and t
HZWE
are specified with C
L
= 5 pF as in part (b) of AC Test Loads and Waveforms. Transition is measured
±
500 mV from steady-state voltage.
6. The internal write time of the memory is defined by the overlap of CS LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
Document #: 38-05268 Rev. **
Page 3 of 9
PRELIMINARY
Switching Characteristics
Over the Operating Range
[3]
(continued)
1851V33-20
Parameter
READ CYCLE
t
RC
t
AA
t
OHA
t
ACS
t
DOE
t
LZOE
t
HZOE
t
LZCS
t
HZCS
t
PD
t
WC
t
SCS
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CS LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
CS LOW to Low Z
[4]
CS HIGH to High Z
[4, 5]
CS HIGH to Power-Down
Write Cycle Time
CS LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z
WE LOW to High Z
[5]
20
17
17
3
2
15
12
2
3
0
12
3
10
20
25
20
20
3
2
20
15
2
3
0
12
0
10
3
12
25
35
30
30
3
2
30
20
2
3
0
3
20
12
0
12
3
20
20
3
25
15
0
25
25
3
35
Description
Min.
Max.
1851V33-25
Min.
Max.
CYM1851V33
1851V33-35
Min.
Max.
Unit
ns
35
35
18
15
15
35
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
15
ns
WRITE CYCLE
[6]
Switching Waveforms
Read Cycle No. 1
[7,8]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Notes:
7. WE is HIGH for read cycle.
8. Device is continuously selected, CS = V
IL
, and OE= V
IL
.
Document #: 38-05268 Rev. **
Page 4 of 9
PRELIMINARY
Switching Waveforms
(continued)
Read Cycle No. 2
[7,9]
CYM1851V33
t
RC
CS
t
ACS
OE
t
DOE
t
LZOE
HIGH IMPEDANCE
DATA OUT
t
LZCS
t
PU
V
CC
SUPPLY
CURRENT
50%
DATA VALID
t
PD
ICC
50%
ISB
t
HZOE
t
HZCS
HIGH
IMPEDANCE
Write Cycle No. 1 (WE Controlled)
[6]
t
WC
ADDRESS
t
SCS
CS
t
AW
t
SA
WE
t
SD
DATA IN
DATA VALID
t
HZWE
DATA OUT
DATA UNDEFINED
t
LZWE
HIGH IMPEDANCE
t
HD
t
PWE
t
HA
Note:
9. Address valid prior to or coincident with CS transition LOW.
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