IS61VPS12836A-250B3 datasheet, PDF

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IS61VPS12836A-250B3: DescriptionCache SRAM, 128KX36, 2.6ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, PLASTIC, BGA-165; Categorystorage storage; File Size541KB，26 Pages; ManufacturerIntegrated Silicon Solution ( ISSI )

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IS61VPS12836A-250B3 Overview

Cache SRAM, 128KX36, 2.6ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, PLASTIC, BGA-165

IS61VPS12836A-250B3 Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	Integrated Silicon Solution ( ISSI )
Parts packaging code	BGA
package instruction	TBGA, BGA165,11X15,40
Contacts	165
Reach Compliance Code	compliant
ECCN code	3A991.B.2.A
Maximum access time	2.6 ns
Other features	PIPELINED ARCHITECTURE
Maximum clock frequency (fCLK)	250 MHz
I/O type	COMMON
JESD-30 code	R-PBGA-B165
JESD-609 code	e0
length	15 mm
memory density	4718592 bit
Memory IC Type	CACHE SRAM
memory width	36
Number of functions	1
Number of terminals	165
word count	131072 words
character code	128000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	128KX36
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	TBGA
Encapsulate equivalent code	BGA165,11X15,40
Package shape	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	2.5 V
Certification status	Not Qualified
Maximum seat height	1.2 mm
Maximum standby current	0.07 A
Minimum standby current	2.38 V
Maximum slew rate	0.225 mA
Maximum supply voltage (Vsup)	2.75 V
Minimum supply voltage (Vsup)	2.375 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	13 mm

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IS61(64)LPS12832A

IS61(64)LPS12836A IS61(64)VPS12836A

IS61(64)LPS25618A IS61(64)VPS25618A

128K x 32, 128K x 36, 256K x 18

FEATURES

• Internal self-timed write cycle

• Individual Byte Write Control and Global Write

• Clock controlled, registered address, data and

control

• Burst sequence control using MODE input

• Three chip enable option for simple depth ex-

pansion and address pipelining

• Common data inputs and data outputs

• Auto Power-down during deselect

• Single cycle deselect

• Snooze MODE for reduced-power standby

• Power Supply

LPS: V

3.3V + 5%,

ddq

3.3V/2.5V + 5%

VPS: V

2.5V + 5%,

ddq

2.5V + 5%

• JEDEC 100-Pin QFP, 119-ball and 165-ball

BGA packages

• Automotive temperature available

• Lead Free available

DECEMBER 2013

4 Mb SYNCHRONOUS PIPELINED, SINgLE CYCLE DESELECT STATIC RAM

DESCRIPTION

The

ISSI

IS61(64)LPS12832A, IS61(64)LPS/VP-

S12836A and IS61(64)LPS/VPS25618A are

high-speed,

low-power synchronous static

RAMs

designed to provide

burstable, high-performance memory for communication

and networking applications. The IS61(64)LPS12832A

organized as 131,072 words by 32 bits.

The IS61(64)LPS/

VPS12836A is organized as 131,072 words by 36 bits.

The IS61(64)LPS/VPS25618A

is organized as 262,144

words by 18 bits. Fabricated with

ISSI

's advanced CMOS

technology, the device integrates a 2-bit burst counter,

high-speed SRAM core, and high-drive capability outputs

into a single monolithic circuit. All synchronous inputs pass

through registers controlled by a positive-edge-triggered

single clock input.

Write cycles are internally self-timed and are initiated by

the rising edge of the clock input. Write cycles can be one

to four bytes wide as controlled by the write control inputs.

Separate byte enables allow individual bytes to be written.

The byte write operation is performed by using the byte

write enable (BWE) input combined with one or more

individual byte write signals (BWx).

In addition, Global

Write (GW)

is available for writing all bytes at one time,

regardless of the byte write controls.

Bursts can be initiated with either ADSP

(Address Status

Processor) or

ADSC

(Address Status Cache Controller)

input pins. Subsequent burst addresses can be gener-

ated internally and controlled by the

ADV

(burst address

advance) input pin.

The mode pin is used to select the burst sequence or-

der, Linear burst is achieved when this pin is tied LOW.

Interleave burst is achieved when this pin is tied HIGH

or left floating.

FAST ACCESS TIME

Symbol

Parameter

Clock Access Time

Cycle Time

Frequency

250

2.6

250

200

3.1

200

Units

MHz

Copyright © 2013 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liabil-

ity arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any

published information and before placing orders for products.

Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause

failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written

assurance to its satisfaction, that:

a.) the risk of injury or damage has been minimized;

b.) the user assume all such risks; and

c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances

Integrated Silicon Solution, Inc.

Rev. H1

12/06/2013

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