Flash PCMCIA Card
FLF Series
High Density FLASH Memory Card
16, 32, 48, 64, 80 MEGABYTE
WEDC’s Flash memory cards - FLF Series - offer
high density linear Flash memory for code and data
storage, high performance disk emulation, mobile PC
and embedded applications.
The WEDC FLF series is based on Intel’s Multi Level
Cell (MLC) Flash memory technology, providing high
density Flash components at significantly lower cost
per megabyte. MLC technology allows for two bits of
information to be stored in a single cell. This leads to
reduced die size and reduced cost per megabyte.
WEDC’s FLF series cards are built with Intel’s 64Mb
components, 28F640J5, with manufacturer/device ID
of 89/15
H
. The FLF series is available in standard
densities of 16, 32, 48 and 64MB.
Additionally, WEDC’s FLF series provides densities
beyond the 64MB density, supported by PCMCIA
standard. These higher densities are based on a
“paging scheme”. By writing a page address to the
Configuration Option Register (address 4000H), an
additional page of memory could be access. The
current FLF series supports densities to 80MB: total
of 2 pages: page 0 := 64MB, page 1 := 16MB.
To provide a 16 bit word wide access and to support
PCMCIA standard, devices are paired on the card.
Therefore, the Flash array is structured in 128K word
(256kB) blocks. Write, read and block erase
operations can be performed as either a word or byte
wide operation.
The FLF series cards conform with the PC Card 95
Standard supported by PCMCIA and JEIDA,
providing electrical and physical compatibility. The
PC Card form factor offers an industry standard
pinout and mechanical outline, allowing density
upgrades without system design changes.
WEDC’s standard cards are shipped with WEDC’s
Flash Logo. Cards are also available with blank
housings (no Logo). The blank housings are available
in both, a recessed (for label) or flat housing. Please
contact WEDC sales representative for further
information on Custom artwork.
PC Card Products
FEATURES
•
Low cost, high density Linear Flash Card
•
Single 5V Supply
- (3V/5V operation is available as option)
•
Based on Intel 28F640J5 (MLC) Components
•
Fast Read Performance
- 250ns Maximum Access Time
- (200ns optional)
•PCMCIA
compatible
- x8/ x16 Data Interface
•
32-Byte Write Buffer
- 6µs per Byte Effective Write Time
•
Cross-Compatible Command Support
- Intel Basic Command Set
- Common Flash Interface (CFI)
- Scaleable Command Set
•
Power-Down Mode
- Reset, Power Down Registers
•
10,000 Erase Cycles per Block
•
128K word symmetrical Block Architecture
•
PC Card Standard Type II Form Factor
Ordering Information
EDI 7P
XXX
FLF
YY SS T ZZ
where
XXX:
016
16MB
032
32MB
048
48MB
064
64MB
080
80MB
YY:
02
based on 28F640J5
With Attribute Memory
WEDC Logo
Blank Housing Type 2
Blank Housing T 2 (Recessed)
Commercial
200ns
250ns
SS:
03
04
05
C
20
25
T:
ZZ:
White Electronic Designs
One Research Drive Westborough, MA 01581
http://www.whiteedc.com
1
FLF Series
July 28. 1999
Block Diagram
N x 28F640J5
Device Pair (N/2 - 1)
CLn
CH0
Device (N-1)
Device (N-2)
(B26)
A1-A23
+
(A1-A25)
A24, A25, B26
B26, (B27..)
D5-D0=Page Number (PN)
SRes
D7
M Res
/WRi
/RDi
CHn
Qn
Device Pair 1
CL1
CH0
CLn
Q2
CH0
Device 3
Device 2
CL0
Q0
Ctrl
At/Reg enable
/REG
Ai
LvReq
D6
D5
- Page Number (PN) -
D4
D3
D2
D1
D0
ADDRESS BUS
(A1-A25)
ADDRESS
BUFFER
A1-A25
Configuration Option Register: A=4000h (Read/Write)
/WE
/OE
control
logic
/CE2
/CE1
SR Clr
Reg Clr
ADDRESS
4008h
Register NAME
Device Pair 0
CL0
CH0
Device 1
Device 0
4000h
4006h
Management
Registers
4004h
4002h
4000h
Config. and Status Reg.
Configuration Option Register
DATA
BUS
Q8-Q15
DATA
BUS
Q0-Q7
0000h
attrib. mem
CIS
E²PROM 2kB
control
Q0-Q7
I/O buffer
DATA
BUS
D8
-
D15
DATA
BUS
D0
-
D7
A0
Reset
220k
reset circuit
C
M Res
SR Clr
Reg Clr
10k
Vcc
D0 - D15
Configuration Option Register: ADRS=4000h
Read/Write
SRes
D7
D7
OPEN
R/B(N-1)
D6
R/BUSY
R/B1
R/B0
OPEN
OPEN
10k
BVD1
BVD2
Vpp2
Vpp1
N.C.
N.C.
Vcc
D7
D2
reserved
D6
D5
D4
D3
PwrDwn
D2
D5-D0
LevelReq (not supported)
Configuration index
D5-D1 reserved
D0
Page Number Config. (PN)
LvReq
D6
D5
- Page Number (PN) -
D4
D3
D2
D1
D0
CD1
CD2
Vcc
GND
WAIT
Vcc
Soft Reset, active High
1=Reset State
0=End Reset State
VS1
VS2
Power On default =0
Configuration Status Register: ADRS=4002h
Read/Write
reserved
D1
D0
Power Down; active High
1 = Place all memory devices in power down mode
0 = normal operation
Power On default=0
/CE1, /CE2,/OE, /WE, /Reg:
pull up
typ 100k
A0, A25, Reset:
pull down typ 100k
R/Busy - Open Drain output (require pull up on host)
Manufacturer ID
Device ID
Intel 89
H
28F640J5 15
H
FLF Flash Card
based on Strata Flash 28F640J5
PC Card Products
White Electronic Designs
One Research Drive Westborough, MA 01581
http://www.whiteedc.com
2
FLF Series
July 28. 1999
Pinout
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
Signal name
GND
DQ3
DQ4
DQ5
DQ6
DQ7
CE1#
A10
OE#
A11
A9
A8
A13
A14
WE#
RDY/BSY#
Vcc
Vpp1
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
WP
GND
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
I
I
I
I
O
Function
Ground
Data bit 3
Data bit 4
Data bit 5
Data bit 6
Data bit 7
Card enable 1
Address bit 10
Output enable
Address bit 11
Address bit 9
Address bit 8
Address bit 13
Address bit 14
Write Enable
Ready/Busy
Supply Voltage
Prog. Voltage
Address bit 16
Address bit 15
Address bit 12
Address bit 7
Address bit 6
Address bit 5
Address bit 4
Address bit 3
Address bit 2
Address bit 1
Address bit 0
Data bit 0
Data bit 1
Data bit 2
Write Potect
Ground
Active
Pin
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
Signal name
GND
CD1#
DQ11
DQ12
DQ13
DQ14
DQ15
CE2#
VS1
RFU
RFU
A17
A18
A19
A20
A21
Vcc
Vpp2
A22
A23
A24
A25
VS2
RST
Wait#
RFU
REG#
BVD2
BVD1
DQ8
DQ9
DQ10
CD2#
GND
I/O
O
I/O
I/O
I/O
I/O
I
I
O
Function
Ground
Card Detect 1
Data bit 11
Data bit 12
Data bit 13
Data bit 14
Data bit 15
Card Enable 2
Voltage Sense 1
Reserved
Reserved
Address bit 17
Address bit 18
Address bit 19
Address bit 20
Address bit 21
Supply Voltage
Prog. Voltage
Address bit 22
Address bit 23
Address bit 24
Address bit 25
Voltage Sense 2
Card Reset
Extended Bus cycle
Reserved
Attrib Mem Select
Bat. Volt. Detect 2
Bat. Volt. Detect 1
Data bit 8
Data bit 9
Data bit 10
Card Detect 2
Ground
Active
LOW
LOW
LOW
LOW
NC (2)
LOW
LOW(1)
N.C.
I
I
I
I
I
N.C.
I
I
I
I
I
I
I
I
I
I
I
I/O
I/O
I/O
O
I
I
I
I
O
I
O
I
O
O
I/O
I/O
O
O
N.C.
HIGH
LOW(3)
(3)
(3)
HIGH
LOW
Notes:
1) RDY/BSY signal is an open drain type output, pull-up resistors are required on the host side
2)VS1 is connected to GND for 3.3V/5V cards and N.C. for 5V only cards
3)Wait#, BVD1 and BVD2 are internally connected to Vcc by resistors for compatibility
Mechanical
1.0mm
±0.05
0.039’
1.6mm
±
0.05
0.063”
85.6mm
±
0.20
3.370”
3.0mm
MIN.
Substrate area
54.0mm
±
0.10
2.126”
1.0mm
±0.05
0.039’
10.0mm MIN
0.400”
Interconnect area
5.0mm
±
T1
0.197”
PC Card Products
White Electronic Designs
One Research Drive Westborough, MA 01581
http://www.whiteedc.com
3
FLF Series
July 28. 1999
Card Signal Description
Symbol
A0 - A25
DQ0 - DQ15
CE1#, CE2#
OE#
WE#
RDY/BSY#
Type
INPUT
INPUT/OUTPUT
INPUT
INPUT
INPUT
OUTPUT
Name and Function
ADDRESS INPUTS:
A0 through A25 enable direct addressing of up
to 64MB of memory on the card. Signal A0 is not used in word access
mode. A25 is the most significant bit
DATA INPUT/OUTPUT:
DQ0 THROUGH DQ15 constitute the
bi-directional databus. DQ15 is the MSB.
CARD ENABLE 1 AND 2:
CE1# enables even byte accesses, CE2#
enables odd byte accesses. Multiplexing A0, CE1# and CE2# allows 8-
bit hosts to access all data on DQ0 - DQ7 (see truth table).
OUTPUT ENABLE:
Active low signal gating read data from the
memory card.
WRITE ENABLE:
Active low signal gating write data to the memory
card.
READY/BUSY OUTPUT:
Indicates status of internally timed erase
or program algorithms. A high output indicates that the card is ready to
accept accesses. A low output indicates that one or more devices in the
memory card are busy with internally timed erase or write activities.
CARD DETECT 1 and 2:
Provide card insertion detection. These
signals are internally connected to ground on the card. The host shall
monitor these signals to detect card insertion. Pulled up on host side.
WRITE PROTECT:
Write protect reflects the status of the Write
Protect switch on the memory card. WP set to high = write protected,
providing internal hardware write lockout to the Flash array.
If card does not include optional write protect switch, this signal will be
pulled low internally indicating write protect = "off".
PROGRAMMING VOLTAGES:
Not connected for 5V only card.
CARD POWER SUPPLY:
5.0V for all internal circuitry.
CARD GROUND
ATTRIBUTE MEMORY SELECT:
Active low signal, enables
access to attribute memory space, occupied by the Card Information
Structure (CIS) and Card Registers.
RESET:
Active high signal for placing card in Power-on default state.
Reset can be used as a Power-Down control for the memory array.
WAIT:
This signal is pulled high internally for compatibility. No wait
states are generated.
BATTERY VOLTAGE DETECT:
These signals are pulled high to
maintain SRAM card compatibility.
VOLTAGE SENSE:
Notifies the host socket of the card's VCC
requirements. VS1 and VS2 are open to indicate a 5V card.
RESERVED FOR FUTURE USE
NO INTERNAL CONNECTION TO CARD:
pin may be driven
or left floating.
Common Memory
Attribute Memory
CD1#, CD2#
WP
OUTPUT
OUTPUT
VPP1, VPP2
VCC
GND
REG#
RST
WAIT#
BVD1, BVD2
VS1, VS2
RFU
N.C.
N.C.
INPUT
INPUT
OUTPUT
OUTPUT
OUTPUT
Functional Truth Table
READ function
Function Mode
Standby Mode
Byte Access (8 bits)
Word Access (16 bits)
Odd-Byte Only Access
WRITE function
/CE2 /CE1
H
H
H
L
H
L
L
L
L
H
H
H
H
L
L
H
L
L
L
H
A0
X
L
H
X
X
X
L
H
X
X
/OE
X
L
L
L
L
X
H
H
H
H
/WE
X
H
H
H
H
X
L
L
L
L
/REG D15-D8
D7-D0
X
High-Z
High-Z
H
High-Z
Even-Byte
H
High-Z
Odd-Byte
H
Odd-Byte Even-Byte
H
Odd-Byte
High-Z
X
H
H
H
H
X
X
X
Even-Byte
X
Odd-Byte
Odd-Byte Even-Byte
Odd-Byte
X
/REG D15-D8
D7-D0
X
High-Z
High-Z
L
High-Z Even-Byte
L
High-Z Not Valid
L
Not Valid Even-Byte
L
Not Valid
High-Z
X
L
L
L
L
X
X
X
X
X
X
Even-Byte
X
Even-Byte
X
Standby Mode
Byte Access (8 bits)
Word Access (16 bits)
Odd-Byte Only Access
PC Card Products
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4
FLF Series
July 28. 1999
Card Interface
The FLF series flash card complies with PC Card standard (PCMCIA, March 1997). While maintaining PCMCIA
compatibility, the FLF series card has integrated special features to extend functionality.
Card has built in 2 control registers:
- Configuration Option Register (COR)
Address = 4000
h
- Configuration and Status Register (CSR)
Address = 4002
h
COR register:
provide a soft reset function (bit D7) and additional page register (bit D0) to extend card capacity
beyond 64MB.
SReset
As defined by PCMCIA, setting the SReset bit to 1, places the card in the reset state. During this state
all memory devices are place in power down mode, minimizing power consumption. Returning this bit
to 0 leaves the reset cycle and place the card in the same condition as following a power up or
hardware reset. This bit must be cleared to 0, to access any device on the card.
Complete soft reset cycle must consist of a 2 step write sequence to the SReset bit:
1. Initialization: write 1 to SReset
- reset cycle begin
- memory devices enters Power-Down mode aborting all operations and clearing all registers.
2. Write 0 to SReset
- Reset cycle ends
- memory devices and registers enters power on default state
Card can be place in Power Down mode by activating Reset signal (pin58) or by controlling
the bit D2 in CSR register.
LevlRequest
Not supported
Configuration Index
Configuration Index bits (D0 - D5) are defined to provide address extension bits -page address, to
extend card capacity beyond 64MB.
Only bit D0 is supported:
- D0 set to 0 selects
page 0
- D0 set to 1 selects:
page 1
D0 is set to the value of 0, during power on or any reset.
CSR register:
provide a power control of memory array. Only bit D2 is supported; all other bits are “don’t care”
PwrDwn
Writing 1 to PwrDwn bit (D2) forces each memory device on the card into a reset/power down mode
by asserting all the devices RP# pins. Writing 0 to the bit returns the array to stand by mode.
Card Information Structure (CIS) contains information about Registers addressing and Memory structure.
Cards with memory capacity < 64MB do not support Configuration Index bits.
Note: - reading from undefined address location or unsupported bits will return random data
- writing to undefined address location may result in card malfunctioning due to limited address
decoding
- see block diagram for more details about control registers
PC Card Products
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One Research Drive Westborough, MA 01581
http://www.whiteedc.com
5
FLF Series
July 28. 1999
stm32/stm8
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