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ADSP-3128ASG/883B

Description
16-BIT, DSP-PIPELINE REGISTER, CPGA144, CERAMIC, PGA-144
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size2MB,28 Pages
ManufacturerRochester Electronics
Websitehttps://www.rocelec.com/
Download Datasheet Parametric Compare View All

ADSP-3128ASG/883B Overview

16-BIT, DSP-PIPELINE REGISTER, CPGA144, CERAMIC, PGA-144

ADSP-3128ASG/883B Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerRochester Electronics
Parts packaging codePGA
package instructionPGA,
Contacts144
Reach Compliance Codeunknown
boundary scanNO
maximum clock frequency20 MHz
External data bus width16
JESD-30 codeS-CPGA-P144
JESD-609 codee0
length40 mm
low power modeNO
Humidity sensitivity levelNOT SPECIFIED
Number of terminals144
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Output data bus width16
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codePGA
Package shapeSQUARE
Package formGRID ARRAY
Peak Reflow Temperature (Celsius)NOT SPECIFIED
Certification statusMILITARY
Maximum seat height4.19 mm
Maximum supply voltage5.5 V
Minimum supply voltage4.5 V
Nominal supply voltage5 V
surface mountNO
Temperature levelMILITARY
Terminal surfaceTIN LEAD
Terminal formPIN/PEG
Terminal pitch2.54 mm
Terminal locationPERPENDICULAR
Maximum time at peak reflow temperatureNOT SPECIFIED
width40 mm
uPs/uCs/peripheral integrated circuit typeDSP PERIPHERAL, PIPELINE REGISTER
Base Number Matches1

ADSP-3128ASG/883B Related Products

ADSP-3128ASG/883B ADSP-3128AJG
Description 16-BIT, DSP-PIPELINE REGISTER, CPGA144, CERAMIC, PGA-144 16-BIT, DSP-PIPELINE REGISTER, CPGA144, CERAMIC, PGA-144
Is it lead-free? Contains lead Contains lead
Is it Rohs certified? incompatible incompatible
Maker Rochester Electronics Rochester Electronics
Parts packaging code PGA PGA
package instruction PGA, PGA,
Contacts 144 144
Reach Compliance Code unknown unknown
boundary scan NO NO
maximum clock frequency 20 MHz 20 MHz
External data bus width 16 16
JESD-30 code S-CPGA-P144 S-CPGA-P144
JESD-609 code e0 e0
length 40 mm 40 mm
low power mode NO NO
Humidity sensitivity level NOT SPECIFIED NOT SPECIFIED
Number of terminals 144 144
Maximum operating temperature 125 °C 70 °C
Output data bus width 16 16
Package body material CERAMIC, METAL-SEALED COFIRED CERAMIC, METAL-SEALED COFIRED
encapsulated code PGA PGA
Package shape SQUARE SQUARE
Package form GRID ARRAY GRID ARRAY
Peak Reflow Temperature (Celsius) NOT SPECIFIED NOT SPECIFIED
Certification status MILITARY COMMERCIAL
Maximum seat height 4.19 mm 4.19 mm
Maximum supply voltage 5.5 V 5.25 V
Minimum supply voltage 4.5 V 4.75 V
Nominal supply voltage 5 V 5 V
surface mount NO NO
Temperature level MILITARY COMMERCIAL
Terminal surface TIN LEAD TIN LEAD
Terminal form PIN/PEG PIN/PEG
Terminal pitch 2.54 mm 2.54 mm
Terminal location PERPENDICULAR PERPENDICULAR
Maximum time at peak reflow temperature NOT SPECIFIED NOT SPECIFIED
width 40 mm 40 mm
uPs/uCs/peripheral integrated circuit type DSP PERIPHERAL, PIPELINE REGISTER DSP PERIPHERAL, PIPELINE REGISTER
Base Number Matches 1 1
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