ADSP-3128AJG datasheet, PDF - EEWORLD Datasheet

ADSP-3128AJG: Description16-BIT, DSP-PIPELINE REGISTER, CPGA144, CERAMIC, PGA-144; CategoryThe embedded processor and controller Microcontrollers and processors; File Size2MB，28 Pages; ManufacturerRochester Electronics; Websitehttps://www.rocelec.com/

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ADSP-3128AJG Overview

16-BIT, DSP-PIPELINE REGISTER, CPGA144, CERAMIC, PGA-144

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	Rochester Electronics
Parts packaging code	PGA
package instruction	PGA,
Contacts	144
Reach Compliance Code	unknown
boundary scan	NO
maximum clock frequency	20 MHz
External data bus width	16
JESD-30 code	S-CPGA-P144
JESD-609 code	e0
length	40 mm
low power mode	NO
Humidity sensitivity level	NOT SPECIFIED
Number of terminals	144
Maximum operating temperature	70 °C
Minimum operating temperature
Output data bus width	16
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	PGA
Package shape	SQUARE
Package form	GRID ARRAY
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Certification status	COMMERCIAL
Maximum seat height	4.19 mm
Maximum supply voltage	5.25 V
Minimum supply voltage	4.75 V
Nominal supply voltage	5 V
surface mount	NO
Temperature level	COMMERCIAL
Terminal surface	TIN LEAD
Terminal form	PIN/PEG
Terminal pitch	2.54 mm
Terminal location	PERPENDICULAR
Maximum time at peak reflow temperature	NOT SPECIFIED
width	40 mm
uPs/uCs/peripheral integrated circuit type	DSP PERIPHERAL, PIPELINE REGISTER
Base Number Matches	1

	ADSP-3128AJG	ADSP-3128ASG/883B
Description	16-BIT, DSP-PIPELINE REGISTER, CPGA144, CERAMIC, PGA-144	16-BIT, DSP-PIPELINE REGISTER, CPGA144, CERAMIC, PGA-144
Is it lead-free?	Contains lead	Contains lead
Is it Rohs certified?	incompatible	incompatible
Maker	Rochester Electronics	Rochester Electronics
Parts packaging code	PGA	PGA
package instruction	PGA,	PGA,
Contacts	144	144
Reach Compliance Code	unknown	unknown
boundary scan	NO	NO
maximum clock frequency	20 MHz	20 MHz
External data bus width	16	16
JESD-30 code	S-CPGA-P144	S-CPGA-P144
JESD-609 code	e0	e0
length	40 mm	40 mm
low power mode	NO	NO
Humidity sensitivity level	NOT SPECIFIED	NOT SPECIFIED
Number of terminals	144	144
Maximum operating temperature	70 °C	125 °C
Output data bus width	16	16
Package body material	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED
encapsulated code	PGA	PGA
Package shape	SQUARE	SQUARE
Package form	GRID ARRAY	GRID ARRAY
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	NOT SPECIFIED
Certification status	COMMERCIAL	MILITARY
Maximum seat height	4.19 mm	4.19 mm
Maximum supply voltage	5.25 V	5.5 V
Minimum supply voltage	4.75 V	4.5 V
Nominal supply voltage	5 V	5 V
surface mount	NO	NO
Temperature level	COMMERCIAL	MILITARY
Terminal surface	TIN LEAD	TIN LEAD
Terminal form	PIN/PEG	PIN/PEG
Terminal pitch	2.54 mm	2.54 mm
Terminal location	PERPENDICULAR	PERPENDICULAR
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED
width	40 mm	40 mm
uPs/uCs/peripheral integrated circuit type	DSP PERIPHERAL, PIPELINE REGISTER	DSP PERIPHERAL, PIPELINE REGISTER
Base Number Matches	1	1

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