Temperature ranges as follows: A Version, –40°C to +125°C; K Version, 0°C to 125°C.
2
Specifications apply after calibration.
3
SNR calculation includes distortion and noise components.
4
All digital inputs at DGND except for
CONVST, SLEEP, CAL,
and
SYNC
at DV
DD
. No load on the digital outputs. Analog inputs at AGND.
5
CLKIN at DGND when external clock off. All digital inputs at DGND except for
CONVST, SLEEP, CAL,
and
SYNC
at DV
DD
. No load on the digital outputs.
Analog inputs at AGND.
6
The offset and gain calibration spans are defined as the range of offset and gain errors that the AD7851 can calibrate. Note also that these are voltage spans and are
not absolute voltages (i.e., the allowable system offset voltage presented at AIN(+) for the system offset error to be adjusted out will be AIN(–)
±
0.05
×
V
REF
, and the
allowable system full-scale voltage applied between AIN(+) and AIN(–) for the system full-scale voltage error to be adjusted out will be V
REF
±
0.025
×
V
REF
). This is
explained in more detail in the Calibration section of the data sheet.
Specifications subject to change without notice.
–4–
REV. B
AD7851
TIMING SPECIFICATIONS
1
(AV
Parameter
f
CLKIN2
f
SCLK3
t
1 4
t
2
t
CONVERT
t
3
t
4
t
5 5
t
5A5
t
6 5
t
7
t
8
t
9 6
t
106
t
11
t
11A
t
127
t
13
t
148
t
15
t
16
t
CAL9
t
CAL19
t
CAL29
t
DELAY
Limit at T
MIN
, T
MAX
(A, K Versions)
500
7
10
f
CLK IN
100
50
3.25
–0.4 t
SCLK
±
0.4 t
SCLK
0.6 t
SCLK
30
30
45
30
20
0.4 t
SCLK
0.4 t
SCLK
30
30/0.4 t
SCLK
50
50
90
50
2.5 t
CLKIN
2.5 t
CLKIN
41.7
37.04
4.63
65
DD
=
DV
DD
= 5.0 V
5%; f
CLKIN
= 6 MHz, T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
Descriptions that refer to SCLK↑ (rising) or SCLK↓ (falling) edges are with the POLARITY pin HIGH. For the POLARITY pin
LOW, then the opposite edge of SCLK will apply.
Unit
kHz min
MHz max
MHz max
MHz max
ns min
ns max
µs
max
ns min
ns min/max
ns min
ns max
ns max
ns max
ns min
ns min
ns min
ns min
ns min
ns min/max
ns max
ns max
ns max
ns max
ns max
ns max
ms typ
ms typ
ms typ
ns max
Description
Master Clock Frequency
Interface Modes 1, 2, 3 (External Serial Clock)
Interface Modes 4, 5 (Internal Serial Clock)
CONVST
Pulse Width
CONVST↓
to BUSY↑ Propagation Delay
Conversion Time = 20 t
CLKIN
SYNC↓
to SCLK↓ Setup Time (Noncontinuous SCLK Input)
SYNC↓
to SCLK↓ Setup Time (Continuous SCLK Input)
SYNC↓
to SCLK↓ Setup Time, Interface Mode 4 Only
Delay from
SYNC↓
until DOUT Three-State Disabled
Delay from
SYNC↓
until DIN Three-State Disabled
Data Access Time after SCLK↓
Data Setup Time prior to SCLK↑
Data Valid to SCLK Hold Time
SCLK High Pulse Width (Interface Modes 4 and 5)
SCLK Low Pulse Width (Interface Modes 4 and 5)
SCLK↑ to
SYNC↑
Hold Time (Noncontinuous SCLK)
(Continuous SCLK) Does Not Apply to Interface Mode 3
SCLK↑ to
SYNC↑
Hold Time
Delay from
SYNC↑
until DOUT Three-State Enabled
Delay from SCLK↑ to DIN Being Configured as Output
Delay from SCLK↑ to DIN Being Configured as Input
CAL↑
to BUSY↑ Delay
CONVST↓
to BUSY↑ Delay in Calibration Sequence
Full Self-Calibration Time, Master Clock Dependent
(250026 t
CLKIN
)
Internal DAC Plus System Full-Scale Calibration Time, Master Clock
Dependent (222228 t
CLKIN
)
System Offset Calibration Time, Master Clock Dependent
(27798 t
CLKIN
)
Delay from CLK to SCLK
NOTES
1
Sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD
) and timed from a voltage level of 1.6 V. See
Table X and timing diagrams for different interface modes and calibration.
2
Mark/space ratio for the master clock input is 40/60 to 60/40.
3
For Interface Modes 1, 2, 3, the SCLK maximum frequency will be 10 MHz. For Interface Modes 4 and 5, the SCLK will be an output and the frequency will be f
CLKIN
.
4
The
CONVST
pulse width will only apply for normal operation. When the part is in power-down mode, a different
CONVST
pulse width will apply (see Power-
Down section).
5
Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V.
6
For self-clocking mode (Interface Modes 4, 5), the nominal SCLK high and low times will be 0.5 t
SCLK
= 0.5 t
CLKIN
.
7
The time t
12
is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that t
12
as quoted in the timing characteristics is the true bus
relinquish time of the part and is independent of the bus loading.
8
The time t
14
is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time quoted in the timing characteristics is the true
delay of the part in turning off the output drivers and configuring the DIN line as an input. Once this time has elapsed , the user can drive the DIN line knowing
that a bus conflict will not occur.
9
The typical time specified for the calibration times is for a master clock of 6 MHz.
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