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QL7180-4PS484C

Description
Field Programmable Gate Array, 4032 CLBs, CMOS, PBGA484, 23 X 23 MM, 2.13 MM HEIGHT, 1 MM PITCH, PLASTIC, MS-034AAJ-1, BGA-484
CategoryProgrammable logic devices    Programmable logic   
File Size714KB,44 Pages
ManufacturerQuickLogic Corporation
Websitehttps://www.quicklogic.com
Download Datasheet Parametric View All

QL7180-4PS484C Overview

Field Programmable Gate Array, 4032 CLBs, CMOS, PBGA484, 23 X 23 MM, 2.13 MM HEIGHT, 1 MM PITCH, PLASTIC, MS-034AAJ-1, BGA-484

QL7180-4PS484C Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerQuickLogic Corporation
Parts packaging codeBGA
package instructionBGA, BGA484,22X22,40
Contacts484
Reach Compliance Codecompliant
ECCN code3A001.A.7.B
Other featuresMAXIMUM GATES UPTO 662208
Combined latency of CLB-Max2.1311 ns
JESD-30 codeS-PBGA-B484
length23 mm
Humidity sensitivity level3
Configurable number of logic blocks4032
Number of terminals484
Maximum operating temperature70 °C
Minimum operating temperature
organize4032 CLBS
Package body materialPLASTIC/EPOXY
encapsulated codeBGA
Encapsulate equivalent codeBGA484,22X22,40
Package shapeSQUARE
Package formGRID ARRAY
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply2.5,2.5/3.3 V
Programmable logic typeFIELD PROGRAMMABLE GATE ARRAY
Certification statusNot Qualified
Maximum seat height2.34 mm
Maximum supply voltage2.7 V
Minimum supply voltage2.3 V
Nominal supply voltage2.5 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal formBALL
Terminal pitch1 mm
Terminal locationBOTTOM
Maximum time at peak reflow temperatureNOT SPECIFIED
width23 mm
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2.5 V V
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, 2.5/3.3 V Drive Capable I/O
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4,032 Logic Cells
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583,008 Max System Gates
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Up to 506 I/O Pins
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Nine Global Clock Networks:
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One Dedicated
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Eight Programmable
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20 Quad-Net Networks—five per Quadrant
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16 I/O Control—two per I/O Bank
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Four phase locked loops
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Thirty-six 2,304-bit Dual Port High
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ECUs provide integrated Multiply, Add, and
Accumulate Functions.
Performance SRAM Blocks
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82,900 RAM Bits
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RAM/ROM/FIFO Wizard for Automatic
Configuration
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Configurable and Cascadable
PLL
Memory - Dual Port RAM
Embedded Computational Units
PLL
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High performance Enhanced I/O (EIO)—
less than 3 ns Tco
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Programmable Slew Rate Control
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Programmable I/O Standards:
‡
LVTTL, LVCMOS, PCI, GTL+, SSTL2,
and SSTL3
‡
Eight Independent I/O Banks
‡
Three Register Configurations: Input,
Output, and Output Enable
High Speed Logic Cells
583K Gates
PLL
Memory - Dual Port RAM
PLL
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