reducing the number of circuit board layers and shielding
that are traditionally required to pass EMI regulations.
The P2040B uses the most efficient and optimized
modulation
profile
approved
by
the
FCC
and
is
implemented in a proprietary all digital method.
The P2040B modulates the output of a single PLL in order
to “spread” the bandwidth of a synthesized clock and, more
importantly,
harmonics.
This results in significantly lower system EMI compared to
the typical narrow band signal produced by oscillators and
most frequency generators. Lowering EMI by increasing a
signal’s bandwidth is called “spread spectrum clock
generation”.
decreases
the
peak
amplitudes
of
its
Applications
The P2040B is targeted towards digital flat panel
applications for Notebook PCs, Palm-size PCs, Office
Automation Equipments and LCD Monitors.
Product Description
The P2040B is a selectable spread spectrum frequency
modulator designed specifically for digital flat panel
applications.
The
P2040B
reduces
electromagnetic
interference (EMI) at the clock source which provides
system wide reduction of EMI of all clock dependent
signals.
The P2040B allows significant system cost savings by
Block Diagram
SR0 CP1 CP0 SSON#
V
DD
Modulation
CLKIN
Frequency
Divider
Feedback
Divider
PLL
Phase
Detector
Loop
Filter
VCO
Output
Divider
ModOUT
V
SS
PulseCore Semiconductor Corporation
1715 S. Bascom Ave Suite 200, Campbell, CA 95008
•
Tel: 408-879-9077
•
Fax: 408-879-9018
www.pulsecoresemi.com
Notice: The information in this document is subject to change without notice.
November 2006
rev 0.2
Pin Configuration
CLKIN
CP0
CP1
V
SS
1
2
3
4
8
7
6
5
V
DD
SR0
ModOUT
SSON#
P2040B
P2040B
Deviations and Modulation Rate Table
CP0
0
0
0
0
1
1
1
1
CP1
0
0
1
1
0
0
1
1
SR0
0
1
0
1
0
1
0
1
Spreading Range (+/- %)
32.5MHz
0.56
1.94
1.36
1.92
1.24
1.91
0.91
1.47
54MHz
1.05
1.68
1.05
1.68
0.81
1.29
0.45
0.71
65MHz
1.00
1.56
1.00
1.56
0.66
1.02
0.34
0.54
81MHz
0.98
1.48
0.92
1.48
0.40
0.74
0.05
0.36
Modulation Rate
(Fin/40) * 62.49KHz
(Fin/40) * 62.49KHz
(Fin/40) * 62.49KHz
(Fin/40) * 62.49KHz
(Fin/40) * 62.49KHz
(Fin/40) * 62.49KHz
(Fin/40) * 62.49KHz
(Fin/40) * 62.49KHz
Pin Description
Pin#
1
2
3
4
5
6
7
8
Pin Name
CLKIN
CP0
CP1
V
SS
SSON#
ModOUT
SR0
V
DD
Type
I
I
I
P
I
O
I
P
Description
External reference frequency input. Connect to externally generated
reference signal.
Digital logic input used to select charge pump current (see Table 1). This
pin has a 100K Ohm internal pull-up resistor.
Digital logic input used to select charge pump current (see Table 1). This
pin has a 100K Ohm internal pull-up resistor.
Ground Connection. Connect to system ground.
Digital logic input used to enable Spread Spectrum function (Active LOW).
Spread Spectrum function enable when LOW. This pin has a 100K Ohm
internal pull-low resistor.
Spectrum Clock output
Digital logic input used to select Spreading Range (see Table 1) This pin
has a 100K Ohm internal pull-up resistor.
Connect to +3.3V
LCD Panel EMI Reduction IC
Notice: The information in this document is subject to change without notice.
2 of 8
November 2006
rev 0.2
Spread Spectrum Selection
P2040B
Table 1 illustrates the possible spread spectrum options. The optimal setting should minimize system EMI to the fullest
without affecting system performance. The spreading is described as a percentage deviation of the center frequency (Note:
the center frequency is the frequency of the external reference input on CLKIN, Pin 1).
Example:
P2040B is designed for high resolution flat panel applications and is able to support panel frequencies from
30MHz to 100MHz. For a 65MHz pixel clock frequency, a spreading selection of CP0 = 0,CP1=1 and SR0=1 gives a
percentage deviation of +/-1.56% (see Table 1). This results in frequency on ModOUT being swept from 64.5MHz to
65.5MHz. This particular example given here is a common EMI reduction method for notebook LCD panel and has already
been implemented by most of the leading OEM and mobile graphic accelerator manufacturers.
Application Schematic for Mobile LCD Graphics Controllers
+3.3V
65MHz from Graphics
Modulation 65MHz signal
with +/- 1.56% Deviation
and Modulation Rate of
101.54 KHz. This signal is
connected back to the
Spread Spectrum input
Pin (SSIN) of the
Graphics Accelerator.
1
2
3
4
CLKIN
CP0
CP1
V
SS
V
DD
SR0
8
7
0.1 µF
ModOUT 6
SSON#
5
P2040B
Digital control for SS
enable or disable
Absolute Maximum Ratings
Symbol
V
DD
, V
IN
T
STG
T
A
T
s
T
J
T
DV
Storage temperature
Operating temperature
Max. Soldering Temperature (10 sec)
Junction Temperature
Static Discharge Voltage
(As per JEDEC STD22- A114-B)
Parameter
Voltage on any pin with respect to Ground
Rating
-0.5 to +4.6
-65 to +125
-40 to +85
260
150
2
Unit
V
°C
°C
°C
°C
KV
Note: These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect
device reliability.
LCD Panel EMI Reduction IC
Notice: The information in this document is subject to change without notice.
3 of 8
November 2006
rev 0.2
DC Electrical Characteristics
Symbol
V
IL
V
IH
I
IL
I
IH
V
OL
V
OH
I
DD
I
CC
V
DD
t
ON
Z
OUT
Input Low voltage
Input High voltage
Input Low current
(100KΩ input pull-up resistor on inputs SR0, CP1and CP0)
Input High current
(100KΩ input pull-low resistor on input SSON#)
Output Low current
Output High current
Static Supply Current
Dynamic Supply Current (3.3V and 15pF loading)
Operating Voltage
Power up time (first locked clock cycle after power up)
Clock Output impedance
V
DD
= 3.3V, I
OL
= 20mA
V
DD
= 3.3V, I
OH
= 20mA
P2040B
Parameter
Min
V
SS
– 0.3
2.0
-
-
-
2.5
-
9
3.0
-
-
Typ
-
-
-
-
-
-
0.6
16
3.3
0.18
50
Max
0.8
V
DD
+ 0.3
-35
35
0.4
-
-
22
3.6
-
-
Unit
V
V
µA
µA
V
V
mA
mA
V
mS
Ω
AC Electrical Characteristics
Symbol
f
IN
f
OUT
t
LH1
t
HL
1
Parameter
Input Frequency
Output Frequency
Output Rise time
Output Fall time
Jitter (cycle to cycle)
Output Duty cycle
Measured at 0.8V to 2.0V
Measured at 2.0V to 0.8V
Min
30
30
0.7
0.6
-
45
Typ
-
-
0.9
0.8
360
50
Max
100
100
1.1
1.0
-
55
Unit
MHz
MHz
nS
nS
pS
%
t
JC
t
D
Note: 1. t
LH
and t
HL
are measured into a capacitive load of 15pF
LCD Panel EMI Reduction IC
Notice: The information in this document is subject to change without notice.
4 of 8
November 2006
rev 0.2
Package Information
8-lead (150-mil) SOIC Package
P2040B
E
H
D
A2
A
θ
e
B
A
1
C
L
D
Dimensions
Symbol
Min
A1
A
A2
B
C
D
E
e
H
L
θ
Inches
Max
0.010
0.069
0.059
0.020
0.010
0.004
0.053
0.049
0.012
0.007
Millimeters
Min
Max
0.10
1.35
1.25
0.31
0.18
4.90 BSC
3.91 BSC
1.27 BSC
6.00 BSC
0.41
0°
1.27
8°
0.25
1.75
1.50
0.51
0.25
0.193 BSC
0.154 BSC
0.050 BSC
0.236 BSC
0.016
0°
0.050
8°
LCD Panel EMI Reduction IC
Notice: The information in this document is subject to change without notice.
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