ACT5260
64-Bit Superscaler Microprocessor
Features
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Full militarized QED RM5260 microprocessor
Dual Issue superscalar QED RISCMark
™
- can issue one
integer and one floating-point instruction per cycle
microprocessor - can issue one integer and one
floating-point instruction per cycle
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100, 133 and 150MHz frequency (200MHz future option)
Consult Factory for latest speeds
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260 Dhrystone2.1 MIPS
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SPECInt95 4.8. SPECfp95 5.1
High performance system interface compatible with R4600,
R4700 and R5000
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64-bit multiplexed system address/data bus for optimum
price/performance up to 100 MHz operating frequency
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High performance write protocols maximize uncached
write bandwidth
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Operates at input system clock multipliers of 2 through 8
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5V tolerant I/O's
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IEEE 1149.1 JTAG boundary scan
Integrated on-chip caches - up to 3.2GBps internal data rate
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16KB instruction - 2 way set associative
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16KB data - 2 way set associative
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Virtually indexed, physically tagged
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Write-back and write-through on per page basis
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Pipeline restart on first double for data cache misses
Integrated memory management unit
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Fully associative joint TLB (shared by I and D translations)
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48 dual entries map 96 pages
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Variable page size (4KB to 16MB in 4x increments)
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Embedded supply de-coupling capacitors and Pll filter
components
High-performance floating point unit - up to 400 MFLOPS
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Single cycle repeat rate for common single precision
operations and some double precision operations
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Two cycle repeat rate for double precision multiply and
double precision combined multiply-add operations
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Single cycle repeat rate for single precision combined
multiply-add operation
MIPS IV instruction set
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Floating point multiply-add instruction increases
performance in signal processing and graphics
applications
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Conditional moves to reduce branch frequency
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Index address modes (register + register)
Embedded application enhancements
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Specialized DSP integer Multiply-Accumulate instruction
and 3 operand multiply instruction
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I and D cache locking by set
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Optional dedicated exception vector for interrupts
Fully static CMOS design with power down logic
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Standby reduced power mode with WAIT instruction
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5 Watts typical at 3.3V, less than 175 mwatts in Standby
208-lead CQFP, cavity-up package (F17)
208-lead CQFP, inverted footprint (F24), Intended to duplicate
the commercial QED footprint
(Consult Factory)
179-pin PGA package (Future
Product)
(P10)
BLOCK DIAGRAM
Phase Lock Loop
Data Set A
Data Tag A
Store Buffer
DTLB Physical
Data Tag B
Instruction Select
Sys AD
Instruction Set A
Integer Instruction Register
Write Buffer
Read Buffer
Data Set B
Instruction Tag B
DBus
FPIBus
Control
Tag
Floating-point
Register File
Unpacker/Packer
Floating point Control
Aux Tag
Load Aligner
Joint TLB
Integer Register File
Integer/Address Adder
Integer Control
Coprocessor 0
DVA
System/Memory
Control
IVA
Data TLB Virtual
IntIBus
Address Buffer
Instruction Tag A
ITLB Physical
Instruction Set B
FP Instruction Register
Floating-point
MAdd, Add, Sub,Cvt
Div, SqRt
Shifter/Store Aligner
Logic Unit
ABus
PC Incrementer
Branch Adder
Instruction TLB Virtual
Integer Multiply, Divide
Program Counter
eroflex Circuit Technology – RISC TurboEngines For The Future © SCD5260 REV A 3/29/99
DESCRIPTION:
The ACT5260 is a highly integrated superscalar
microprocessor that implements a superset of the
MIPS IV Instruction Set Architecture(ISA). It has a
high performance 64-bit integer unit, a high
throughput, fully pipelined 64-bit floating point unit,
an operating system friendly memory management
unit with a 48-entry fully associative TLB, a 16 KByte
2-way set associative instruction cache, a 16 KByte
2-way set associative data cache, and a
high-performance 64-bit system interface. The
ACT5260 can issue both an integer and a floating
point instruction in the same cycle.
The ACT5260 is ideally suited for high-end
embedded
control
applications
such
as
internetworking,
high
performance
image
manipulation, high speed printing, and 3-D
visualization.
Integer Unit
Like the R5000, the ACT5260 implements the
MIPS IV Instruction Set Architecture, and is therefore
fully upward compatible with applications that run on
processors implementing the earlier generation
MIPS I-III instruction sets. Additionally, the ACT5260
includes two implementation specific instructions not
found in the baseline MIPS IV ISA but that are useful
in the embedded market place. Described in detail in
the QED RM5260 datasheet, these instructions are
integer multiply-accumulate and 3-operand integer
multiply.
The ACT5260 integer unit includes thirty-two
general purpose 64-bit registers, a load/store
architecture with single cycle ALU operations (add,
sub, logical, shift) and an autonomous multiply/divide
unit. Additional register resources include: the HI/LO
result registers for the two-operand integer multiply/
divide operations, and the program counter(PC).
HARDWARE OVERVIEW
The ACT5260 offers a high-level of integration
targeted
at
high-performance
embedded
applications. Some of the key elements of the
ACT5260 are briefly described below.
Register File
The ACT5260 has thirty-two general purpose
registers with register location 0 hard wired to zero.
These registers are used for scalar integer
operations and address calculation. The register file
has two read ports and one write port and is fully
bypassed to minimize operation latency in the
pipeline.
Superscalar Dispatch
The ACT5260 has an efficient asymmetric
superscalar dispatch unit which allows it to issue an
integer instruction and a floating-point computation
instruction simultaneously. With respect to
superscalar issue, integer instructions include alu,
branch, load/store, and floating-point load/store,
while floating-point computation instructions include
floating-point add, subtract, combined multiply-add,
converts, etc. In combination with its high throughput
fully pipelined floating-point execution unit, the
superscalar capability of the ACT5260 provides
unparalleled price/performance in computationally
intensive embedded applications.
ALU
The ACT5260 ALU consists of the integer adder/
subtractor, the logic unit, and the shifter. The adder
performs address calculations in addition to
arithmetic operations, the logic unit performs all
logical and zero shift data moves, and the shifter
performs shifts and store alignment operations. Each
of these units is optimized to perform all operations in
a single processor cycle
CPU Registers
Like all MIPS ISA processors, the ACT5260 CPU
has a simple, clean user visible state consisting of 32
general purpose registers, two special purpose
registers for integer multiplication and division, a
program counter, and no condition code bits.
For additional Detail Information regarding the
operation of the Quantum Effect Design (QED)
RISCMark
™
RM5260
™
,
64-Bit
Superscalar
Microprocessor see the latest QED datasheet
(Revision 1.1 July 1998).
Pipeline
For integer operations, loads, stores, and other
non-floating-point operations, the ACT5260 uses the
simple 5-stage pipeline also found in the circuits
R4600, R4700, and R5000. In addition to this
standard pipeline, the ACT5260 uses an extended
seven stage pipeline for floating-point operations.
Like the R5000, the ACT5260 does virtual to physical
translation in parallel with cache access.
Aeroflex Circuit Technology
2
SCD5260 REV A 3/29/99 Plainview NY (516) 694-6700
MCU
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