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Q33310N70010300

Description
CMOS Output Clock Oscillator,
CategoryPassive components    oscillator   
File Size275KB,5 Pages
ManufacturerSeiko Epson Corporation
Environmental Compliance
Download Datasheet Parametric View All

Q33310N70010300 Overview

CMOS Output Clock Oscillator,

Q33310N70010300 Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
Reach Compliance Codeunknown
Other featuresSTANDBY; ENABLE/DISABLE FUNCTION
maximum descent time4 ns
Frequency Adjustment - MechanicalNO
frequency stability25%
Installation featuresSURFACE MOUNT
Number of terminals4
Nominal operating frequency16.589 MHz
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Oscillator typeCMOS
Output load15 pF
physical size3.2mm x 2.5mm x 1.05mm
longest rise time4 ns
Maximum slew rate5 mA
Maximum supply voltage3.6 V
Minimum supply voltage2.7 V
Nominal supply voltage3.3 V
surface mountYES
maximum symmetry55/45 %
technologyCMOS
Base Number Matches1
Clock OSC
SG-310SCN
SG-310SCN 16.589000 MHz J
Product name
Product Number / Ordering code
Q33310N700103xx
Please refer to the 8.Packing information about xx (last 2 digits)
Output waveform CMOS
Pb free / Complies with EU RoHS directive
Reference weight Typ. 26 mg
1.Absolute maximum ratings
Parameter
Symbol
Maximum supply voltage
Storage temperature
Input voltage
Min.
-0.3
-40
-0.3
Typ.
-
-
-
Max.
7
+125
Vcc+0.3
Unit
V
ºC
V
Conditions / Remarks
-
Storage as single product
ST terminal
Vcc-GND
T_stg
Vin
2.Specifications(characteristics)
Parameter
Symbol
Output frequency
Supply voltage
Operating temperature
Frequency tolerance
Current consumption
Stand-by current
Symmetry
Output voltage
Output load condition
Input voltage
Rise time
Fall time
Start-up time
Jitter
Min.
2.7
-40
-25
-
-
45
0.9Vcc
-
-
0.7Vcc
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-3
-10
Typ.
16.589000
3.3
-
-
-
-
-
-
-
-
-
-
-
-
-
0
2.4
2.4
22
5.4
0.51
-
-94
-122
-136
-146
-152
-160
-
-
Max.
3.6
+85
25
5
10.0
55
-
0.1Vcc
15
-
0.3Vcc
4
4
2
-
-
-
-
-
-
-
-
-
-
-
-
-
3
10
Unit
MHz
V
ºC
x10
-6
mA
µA
%
Conditions / Remarks
-
-
T_use
No load condition
ST = GND
50% Vcc Level L_CMOS=<15pF
IOH=-3mA
IOL=3mA
f0
Vcc
T_use
f_tol
Icc
I_std
SYM
V
OH
V
OL
L_CMOS
V
IH
V
IL
t
r
tf
t_str
t
DJ
t
RJ
t
RMS
t
p-p
t
acc
pF
CMOS Load
ST terminal
ST terminal
ns
ns
ms
ps
ps
ps
ps
ps
ps
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
x10
-6
0.2Vcc to 0.8Vcc Level, L_CMOS=15pF
0.2Vcc to 0.8Vcc Level, L_CMOS=15pF
t = 0 at 0.9Vcc
Deterministic Jitter Vcc=3.3
Random Jitter Vcc=3.3V
δ(RMS of total distribution) Vcc=3.3V
Peak to Peak Vcc=3.3V
Accumulated Jitter(δ) n=2 to 50000
cycles
Off set Frequency: 12kHz to 20MHz Vcc=3.3V
Phase jitter
Phase noise
t
PJ
L(f)
-
Off set 10Hz Vcc=3.3V
Off set 100Hz Vcc=3.3V
Off set 1kHz Vcc=3.3V
Off set 10kHz Vcc=3.3V
Off set 100kHz Vcc=3.3V
Off set 1MHz Vcc=3.3V
@+25ºC first year
25℃,10Years
Frequency aging
f_age
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