Function, pinout, and drive compatible with FCT, F
Logic, and AM29520
•
FCT-C speed at 6.0 ns max. (Com’l),
FCT-B speed at 7.5 ns max. (Com’l)
•
Reduced V
OH
(typically = 3.3V) versions of equivalent
FCT functions
•
Edge-rate control circuitry for significantly improved
noise characteristics
•
Power-Off disable feature
•
Matched rise and fall times
•
Fully compatible with TTL input and output logic levels
•
ESD > 2000V
• Sink current
64 mA (Com’l), 32 mA (Mil)
Source current
32 mA (Com’l), 12 mA (Mil)
•
Single and dual pipeline operation modes
•
Multiplexed data inputs and outputs
Functional Description
The FCT520T is a multi-level 8-bit-wide pipeline register. The
device consists of four registers, A1, A2, B1, and B2, which are
configured by the instruction inputs I
0
, I
1
as a single 4-level
pipeline or as two two-level pipelines. The contents of any
register may be read at the multiplexed output at any time by
using the mux-selection controls S
0
and S
1
.
The pipeline register is positive edge triggered and data is
shifted by the rising edge of the clock input. Instruction I=0
selects the four-level pipeline mode. Instruction I=1 selects the
two-level B pipeline while I=2 selects the two-level A pipeline.
I=3 is the HOLD instruction; no shifting is performed by the
clock in this mode.
In the two-level operation mode, the FCT520T data is shifted
from level 1 to level 2 and new data is loaded into level 1.
The outputs are designed with a power-off disable feature to
allow for live insertion of boards.
Logic Block Diagram
8
D
0
–D
7
Pin Configurations
DIP/SOIC/QSOP
Top View
INSTRUCTION
I
0
I
1
CLOCK
REGISTER
CONTROLS
MUX
I
0
I
1
D
0
OCTAL REG
A1
OCTAL REG
B1
D
1
D
2
D
3
D
4
MUX S
0
SEL S
1
OCTAL REG
A2
OCTAL REG
B2
D
5
D
6
D
7
CLK
GND
MUX
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
V
CC
S
0
S
1
Y
0
Y
1
Y
2
Y
3
Y
4
Y
5
Y
6
Y
7
OE
OE
8
Y
0
–Y
7
Pipeline Instruction Table
I=0
I
1
= 0
I
0
= 0
I=1
I
1
= 0
I
0
= 1
I=2
I
1
= 1
I
0
= 0
I
1
= 1
I=3
I
0
= 1
A1
B1
A1
B1
A1
B1
A1
B1
A2
B2
A2
B2
A2
B2
A2
B2
Single four-level
Dual two-level
Hold
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
• CA 95134 • 408-943-2600
May 1994 - Revised March 17, 1997
CY29FCT520T
Output Selection Mux Table
Inputs.
S
1
1
1
0
0
S
0
1
0
1
0
Output
A1
A2
B1
B2
Supply Voltage to Ground Potential................–0.5V to +7.0V
DC Input Voltage ............................................–0.5V to +7.0V
DC Output Voltage..........................................–0.5V to +7.0V
DC Output Current (Maximum Sink Current/Pin) ...... 120 mA
Power Dissipation .......................................................... 0.5W
Static Discharge Voltage ........................................... >2001V
(per MIL-STD-883, Method 3015)
Maximum Ratings
[1, 2]
(Above which the useful life may be impaired. For user
guidelines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied ............................................. –65°C to +135°C
Operating Range
Range
Commercial
Military
[3]
Range
All
All
Ambient
Temperature
–40°C to +85°C
–55°C to +125°C
V
CC
5V
±
5%
5V
±
10%
Electrical Characteristics
Over the Operating Range
Parameter
V
OH
Description
Output HIGH Voltage
Test Conditions
V
CC
=Min., I
OH
=–32 mA
V
CC
=Min., I
OH
=–15 mA
V
CC
=Min., I
OH
=–12 mA
V
OL
V
IH
V
IL
V
H
V
IK
I
I
I
IH
I
IL
I
OZH
I
OZL
I
OS
I
OFF
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Hysteresis
[5]
Input Clamp Diode Voltage
Input HIGH Current
Input HIGH Current
Input LOW Current
Off State HIGH-Level Output
Current
Off State LOW-Level
Output Current
Output Short Circuit Current
[6]
Power-Off Disable
All inputs
V
CC
=Min., I
IN
=–18 mA
V
CC
=Max., V
IN
=V
CC
V
CC
=Max., V
IN
=2.7V
V
CC
=Max., V
IN
=0.5V
V
CC=
Max., V
OUT
=2.7V
V
CC
=Max., V
OUT
= 0.5V
V
CC
=Max., V
OUT
=0.0V
V
CC
=0V, V
OUT
=4.5V
–60
–120
0.2
–0.7
–1.2
5
±1
±1
10
–10
–225
±1
V
CC
=Min., I
OL
=64 mA
V
CC
=Min., I
OL
=32 mA
Com’l
Com’l
Mil
Com’l
Mil
2.0
0.8
Min.
2.0
2.4
2.4
3.3
3.3
0.3
0.3
0.55
0.55
Typ.
[4]
Max.
Unit
V
V
V
V
V
V
V
V
V
µA
µA
µA
µA
µA
mA
µA
Capacitance
[5]
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
Typ.
[4]
5
9
Max.
10
12
Unit
pF
pF
Notes:
1. Unless otherwise noted, these limits are over the operating free-air temperature range.
2. Unused inputs must always be connected to an appropriate logic voltage level, preferably either V
CC
or ground.
3. T
A
is the “instant on” case temperature.
4. Typical values are at V
CC
=5.0V, T
A
=+25°C ambient.
5. This parameter is guaranteed but not tested.
6. Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample
and hold techniques are preferable in order to minimize internal chip heating and more accurately reflect operational values. Otherwise prolonged shorting of
a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence of parameter
tests, I
OS
tests should be performed last.
2
CY29FCT520T
Power Supply Characteristics
Parameter
I
CC
∆I
CC
I
CCD
Description
Quiescent Power Supply Current
Quiescent Power Supply Current
(TTL inputs HIGH)
Dynamic Power Supply Current
[8]
Test Conditions
V
CC
=Max., V
IN
<0.2V,
V
IN
>V
CC
–0.2V
V
CC
=Max., V
IN
=3.4V, f
1
=0, Outputs Open
[7]
V
CC
=Max., One Input Toggling, 50% Duty Cycle,
Outputs Open, OE=GND,
V
IN
<0.2V
or V
IN
>V
CC
–0.2V
V
CC
=Max., 50% Duty Cycle, Outputs Open,
f
0
=10 MHz, One Bit Toggling at f
1
=5 MHz,
OE=GND, V
IN
<0.2V
or V
IN
>V
CC
–0.2V
V
CC
=Max., 50% Duty Cycle, Outputs Open,
f
0
=10 MHz, One Bit Toggling at f
1
=5 MHz,
OE=GND, V
IN
=3.4V or V
IN
=GND
V
CC
=Max., 50% Duty Cycle, Outputs Open,
f
0
=10 MHz, Eight Bits Toggling at f
1
=5 MHz,
OE=GND, V
IN
<0.2V
or V
IN
>V
CC
–0.2V
V
CC
=Max., 50% Duty Cycle, Outputs Open,
f
0
=10 MHz, Eight Bits Toggling at f
1
=5 MHz,
OE=GND, V
IN
=3.4V or V
IN
=GND
Notes:
7. Per TTL driven input (V
IN
=3.4V); all other inputs at V
CC
or GND.
8. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
9. I
C
I
C
= I
CC
+∆I
CC
D
H
N
T
+I
CCD
(f
0
/2 + f
1
N
1
)
I
CC
= Quiescent Current with CMOS input levels
∆I
CC
= Power Supply Current for a TTL HIGH input (V
IN
=3.4V)
D
H
= Duty Cycle for TTL inputs HIGH
N
T
= Number of TTL inputs at D
H
I
CCD
= Dynamic Current caused by an input transition pair (HLH or LHL)
= Clock frequency for registered devices, otherwise zero
f
0
= Input signal frequency
f
1
N
1
= Number of inputs changing at f
1
All currents are in milliamps and all frequencies are in megahertz.
10. Values for these conditions are examples of the I
CC
formula. These limits are guaranteed but not tested.
Typ.
[4]
0.1
0.5
0.06
Max.
0.2
2.0
0.12
Unit
mA
mA
mA/MHz
I
C
Total Power Supply Current
[9]
0.7
1.4
mA
1.2
3.4
mA
2.8
5.6
[10]
mA
5.1
14.3
[10]
mA
3
CY29FCT520T
Switching Characteristics
Over the Operating Range
[11]
FCT520AT
Military
Parameter
t
PLH
t
PHL
t
PLH
t
PHL
t
S
t
H
t
S
t
H
t
PHZ
t
PLZ
t
PZH
t
PZL
t
W
Description
Propagation Delay
Clock to Data Output
Propagation Delay
S
0
, S
1
to Data Output
Set-Up Time Input Data
to Clock
Hold Time Input Data to
Clock
Set-Up Time Instruction
(Reg. Enable) to Clock
Hold Time Instruction
(Reg. Enable) to Clock
Output Disable Time
Output Enable Time
Clock Pulse Width,
[5]
HIGH or LOW
Min.
2.0
2.0
6.0
2.0
6.0
2.0
1.5
1.5
8.0
13.0
16.0
Max.
16.0
15.0
Commercial
Min
2.0
2.0
5.0
2.0
5.0
2.0
1.5
1.5
7.0
12.0
15.0
Max.
14.0
13.0
Min.
2.0
2.0
2.8
2.0
4.5
2.0
1.5
1.5
6.0
7.5
8.0
FCT520BT
Military
Max.
8.0
8.0
Commercial
Min.
2.0
2.0
2.5
2.0
4.0
2.0
1.5
1.5
5.5
7.0
7.5
Max.
7.5
7.5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Fig.
No.
[12]
1, 5
1, 5
4
4
4
4
1, 7, 8
1, 7, 8
5
FCT520CT
Commercial
Parameter
t
PLH
t
PHL
t
PLH
t
PHL
t
S
t
H
t
S
t
H
t
PHZ
t
PLZ
t
PZH
t
PZL
t
W
Description
Propagation Delay Clock to Data Output
Propagation Delay S
0
, S
1
to Data Output
Set-Up Time Input Data to Clock
Hold Time Input Data to Clock
Set-Up Time Instruction (Reg. Enable) to Clock
Hold Time Instruction (Reg. Enable) to Clock
Output Disable Time
Output Enable Time
Clock Pulse Width,
[5]
HIGH or LOW
Min.
2.0
2.0
2.5
2.0
4.0
2.0
1.5
1.5
5.5
6.0
6.0
Max.
6.0
6.0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Fig. No.
[12]
1, 5
1, 5
4
4
4
4
1, 7, 8
1, 7, 8
5
Notes:
11. Minimum limits are guaranteed but not tested on Propagation Delays.
12. See “Parameter Measurement Information” in the General Information section.
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