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XC3S5000-4FGG1156I

Description
Field Programmable Gate Array, 8320 CLBs, 5000000 Gates, 630MHz, 74880-Cell, CMOS, PBGA1156, 35 X 35 MM, LEAD FREE, FBGA-1156
CategoryProgrammable logic devices    Programmable logic   
File Size2MB,217 Pages
ManufacturerXILINX
Websitehttps://www.xilinx.com/
Environmental Compliance  
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XC3S5000-4FGG1156I Overview

Field Programmable Gate Array, 8320 CLBs, 5000000 Gates, 630MHz, 74880-Cell, CMOS, PBGA1156, 35 X 35 MM, LEAD FREE, FBGA-1156

XC3S5000-4FGG1156I Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerXILINX
Parts packaging codeBGA
package instruction35 X 35 MM, LEAD FREE, FBGA-1156
Contacts1156
Reach Compliance Codeunknown
ECCN code3A001.A.7.A
maximum clock frequency630 MHz
Combined latency of CLB-Max0.61 ns
JESD-30 codeS-PBGA-B1156
JESD-609 codee1
length35 mm
Humidity sensitivity level3
Configurable number of logic blocks8320
Equivalent number of gates5000000
Number of entries784
Number of logical units74880
Output times784
Number of terminals1156
organize8320 CLBS, 5000000 GATES
Package body materialPLASTIC/EPOXY
encapsulated codeBGA
Encapsulate equivalent codeBGA1156,34X34,40
Package shapeSQUARE
Package formGRID ARRAY
Peak Reflow Temperature (Celsius)245
power supply1.2,1.2/3.3,2.5 V
Programmable logic typeFIELD PROGRAMMABLE GATE ARRAY
Certification statusNot Qualified
Maximum seat height2.6 mm
Maximum supply voltage1.26 V
Minimum supply voltage1.14 V
Nominal supply voltage1.2 V
surface mountYES
technologyCMOS
Terminal surfaceTin/Silver/Copper (Sn95.5Ag4.0Cu0.5)
Terminal formBALL
Terminal pitch1 mm
Terminal locationBOTTOM
Maximum time at peak reflow temperature40
width35 mm
Base Number Matches1
0
R
Spartan-3 FPGA Family
Data Sheet
0
0
DS099 December 4, 2009
Product Specification
This document includes all four modules of the Spartan
®
-3 FPGA data sheet.
Module 1:
Spartan-3 FPGA Family: Introduction
and Ordering Information
DS099-1 (v2.5) December 4, 2009
Introduction
Features
Architectural Overview
Array Sizes and Resources
User I/O Chart
Ordering Information
Module 3:
Spartan-3 FPGA Family: DC and
Switching Characteristics
DS099-3 (v2.5) December 4, 2009
DC Electrical Characteristics
- Absolute Maximum Ratings
- Supply Voltage Specifications
- Recommended Operating Conditions
- DC Characteristics
Switching Characteristics
- I/O Timing
- Internal Logic Timing
- DCM Timing
- Configuration and JTAG Timing
Module 2:
Spartan-3 FPGA Family: Functional
Description
DS099-2 (v2.5) December 4, 2009
Input/Output Blocks (IOBs)
- IOB Overview
- SelectIO™ Interface I/O Standards
Configurable Logic Blocks (CLBs)
Block RAM
Dedicated Multipliers
Digital Clock Manager (DCM)
Clock Network
Configuration
Module 4:
Spartan-3 FPGA Family: Pinout
Descriptions
DS099-4 (v2.5) December 4, 2009
Pin Descriptions
- Pin Behavior During Configuration
Package Overview
Pinout Tables
- Footprints
IMPORTANT NOTE:
Each module has its own Revision History at the end. Use the PDF "Bookmarks" for easy navigation
in this volume.
© 2003–2009 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other coun-
tries. All other trademarks are the property of their respective owners.
DS099 December 4, 2009
Product Specification
www.xilinx.com
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