Organized as 512Kx32, User Configurable as 1Mx16 or 2Mx8
n
Commercial, Industrial and Military Temperature Ranges
n
TTL Compatible Inputs and Outputs
n
5 Volt Power Supply
n
Low Power CMOS
n
Built-in Decoupling Caps and Multiple Ground Pins for Low
Noise Operation
n
Weight
WS512K32-XH1X - 13 grams typical
WS512K32-XG2TX
1
- 8 grams typical
WS512K32-XG1UX - 5 grams typical
WS512K32-XG1TX - 5 grams typical
WS512K32-XG4TX
1
- 20 grams typical
* 15ns Access Time available only in Commercial and Industrial Temperature.
This speed is not fully characterized and is subject to change without notice.
Note 1: Package Not Recommended For New Design
FIG. 1
PIN CONFIGURATION FOR WS512K32N-XH1X
TOP VIEW
PIN DESCRIPTION
I/O
0-31
A
0-18
WE
1-4
CS
1-4
OE
V
CC
GND
NC
Data Inputs/Outputs
Address Inputs
Write Enables
Chip Selects
Output Enable
Power Supply
Ground
Not Connected
BLOCK DIAGRAM
November 2001 Rev. 9
1
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
WS512K32-XXX
FIG. 2
PIN CONFIGURATION FOR WS512K32-XG4TX
1
TOP VIEW
PIN DESCRIPTION
I/O
0-31
A
0-18
WE
CS
1-4
OE
V
CC
GND
NC
Data Inputs/Outputs
Address Inputs
Write Enables
Chip Selects
Output Enable
Power Supply
Ground
Not Connected
BLOCK DIAGRAM
Note 1: Package Not Recommended For New Design
FIG. 3
PIN CONFIGURATION FOR WS512K32-XG2TX
1
, WS512K32-XG1TX
AND WS512K32-XG1UX
TOP VIEW
PIN DESCRIPTION
I/O
0-31
A
0-18
WE
1-4
CS
1-4
OE
V
CC
GND
NC
Data Inputs/Outputs
Address Inputs
Write Enables
Chip Selects
Output Enable
Power Supply
Ground
Not Connected
The White 68 lead CQFP fills
the same fit and function as the
JEDEC 68 lead CQFJ or 68
PLCC. But the CQFJ has the
TCE and lead inspection
advantage of the CQFP form.
BLOCK DIAGRAM
Note 1: Package Not Recommended For New Design
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
2
WS512K32-XXX
ABSOLUTE MAXIMUM RATINGS
Parameter
Operating Temperature
Storage Temperature
Signal Voltage Relative to GND
Junction Temperature
Supply Voltage
Symbol
T
A
T
STG
V
G
T
J
V
CC
-0.5
Min
-55
-65
-0.5
Max
+125
+150
Vcc+0.5
150
7.0
Unit
°C
°C
V
°C
V
CS
H
L
L
L
OE
X
L
H
X
WE
X
H
H
L
TRUTH TABLE
Mode
Standby
Read
Out Disable
Write
Data I/O
High Z
Data Out
High Z
Data In
Power
Standby
Active
Active
Active
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage
Input High Voltage
Input Low Voltage
Operating Temp (Mil)
Symbol
V
CC
V
IH
V
IL
T
A
Min
4.5
2.2
-0.5
-55
Max
5.5
V
CC
+ 0.3
+0.8
+125
Unit
V
V
V
°C
CAPACITANCE
(T
A
= +25°C)
Parameter
OE capacitance
WE
1-4
capacitance
HIP (PGA)
CQFP G4T
CQFP G2T/G1U/G1T
CS
1-4
capacitance
Data I/O capacitance
Address input capacitance
Symbol
C
OE
C
WE
Conditions
V
IN
= 0 V, f = 1.0 MHz
V
IN
= 0 V, f = 1.0 MHz
Max
50
20
50
20
20
20
50
Unit
pF
pF
C
CS
C
I/O
C
AD
V
IN
= 0 V, f = 1.0 MHz
V
I/O
= 0 V, f = 1.0 MHz
V
IN
= 0 V, f = 1.0 MHz
pF
pF
pF
This parameter is guaranteed by design but not tested.
DC CHARACTERISTICS
(V
CC
= 5.0V, V
SS
= 0V, T
A
= -55°C to +125°C)
Parameter
Input Leakage Current
Output Leakage Current
Operating Supply Current x 32 Mode
Standby Current
Output Low Voltage
Output High Voltage
Symbol
I
LI
I
LO
I
CC x 32
I
SB
V
OL
V
OH
Conditions
V
CC
= 5.5, V
IN
= G
ND
to V
CC
CS = V
IH
, OE = V
IH
, V
OUT
= GND to V
CC
CS = V
IL
, OE = V
IH
, f = 5MHz, Vcc = 5.5
CS = V
IH
, OE = V
IH
, f = 5MHz, Vcc = 5.5
I
OL
= 8mA for 15 - 35ns,
I
OL
= 2.1mA for 45 - 55ns, Vcc = 4.5
I
OH
= -4.0mA for 15 - 35ns,
I
OH
= -1.0mA for 45 - 55ns, Vcc = 4.5
2.4
Min
Max
10
10
660
80
0.4
Units
µA
µA
mA
mA
V
V
NOTE:
DC test conditions: V
IH
= V
CC
-0.3V, V
IL
= 0.3V
DATA RETENTION CHARACTERISTICS
(T
A
= -55°C to +125°C)
Parameter
Data Retention Supply Voltage
Data Retention Current
Low Power Data Retention
Current (WS512K32L-XXX)
Symbol
V
DR
I
CCDR1
I
CCDR2
Conditions
Min
CS
£
V
CC
-0.2V
V
CC
= 3V
V
CC
= 3V
2.0
Max
5.5
28
16
V
mA
mA
Units
3
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
WS512K32-XXX
AC CHARACTERISTICS
(V
CC
= 5.0V, V
SS
= 0V, T
A
= -55°C to +125°C)
Parameter
Read Cycle
Read Cycle Time
Address Access Time
Output Hold from Address Change
Chip Select Access Time
Output Enable to Output Valid
Chip Select to Output in Low Z
Output Enable to Output in Low Z
Chip Disable to Output in High Z
Output Disable to Output in High Z
t
RC
t
AA
t
OH
t
ACS
t
OE
t
CLZ
t
OLZ
1
Symbol
15
-15*
Min
Max
15
0
15
8
2
0
12
12
2
0
0
Min
17
-17
Max
17
0
17
9
2
0
12
12
Min
20
-20
Max
20
0
20
10
2
0
12
12
Min
25
-25
Max
25
0
25
12
4
0
12
12
Min
35
-35
Max
35
0
35
25
4
0
15
15
Min
45
-45
Max
45
0
45
25
4
0
20
20
55
-55
Min
Max
Units
ns
55
55
25
ns
ns
ns
ns
ns
ns
20
20
ns
ns
1
t
CHZ
1
t
OHZ
1
* 15ns Access Time available only in Commercial and Industrial Temperature. This speed is not fully characterized and is subject to change without notice.
1. This parameter is guaranteed by design but not tested.
AC CHARACTERISTICS
(V
CC
= 5.0V, V
SS
= 0V, T
A
= -55°C to +125°C)
Parameter
Write Cycle
Write Cycle Time
Chip Select to End of Write
Address Valid to End of Write
Data Valid to End of Write
Write Pulse Width
Address Setup Time
Address Hold Time
Output Active from End of Write
Write Enable to Output in High Z
Data Hold Time
t
WC
t
CW
t
AW
t
DW
t
WP
t
AS
t
AH
t
OW
t
DH
1
Symbol
15
13
13
10
13
2
0
2
-15*
Min
Max
17
15
15
11
15
2
0
2
8
0
0
-17
Min
Max
20
15
15
12
15
2
0
3
9
0
-20
Min
Max
Min
25
17
17
13
17
2
0
4
11
0
-25
Max
Min
35
25
25
20
25
2
0
4
13
0
-35
Max
45
35
35
25
35
2
5
5
15
0
-45
Min
Max
55
50
50
25
40
2
5
5
20
0
-55
Min Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
20
ns
ns
t
WHZ
1
* 15ns Access Time available only in Commercial and Industrial Temperature. This speed is not fully characterized and is subject to change without notice.
1. This parameter is guaranteed by design but not tested.
2 . The Address Setup Time of minimum 2ns is for the G2T, G1U and H1 packages. t
AS
minimum for the G4T package is 0ns.
FIG. 4
AC TEST CIRCUIT
AC TEST CONDITIONS
Parameter
Input Pulse Levels
Input Rise and Fall
Input and Output Reference Level
Output Timing Reference Level
Typ
V
IL
= 0, V
IH
= 3.0
5
1.5
1.5
Unit
V
ns
V
V
NOTES:
V
Z
is programmable from -2V to +7V.
I
OL
& I
OH
programmable from 0 to 16mA.
Tester Impedance Z
0
= 75 ½.
V
Z
is typically the midpoint of V
OH
and V
OL
.
I
OL
& I
OH
are adjusted to simulate a typical resistive load circuit.
ATE tester includes jig capacitance.
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
4
WS512K32-XXX
FIG. 5
TIMING WAVEFORM - READ CYCLE
FIG. 6
WRITE CYCLE - WE CONTROLLED
FIG. 7
WRITE CYCLE - CS CONTROLLED
WS32K32-XHX
5
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
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