HB52RD168GB-F
EO
Description
Features
128 MB Unbuffered SDRAM Micro DIMM
16-Mword
×
64-bit, 100 MHz Memory Bus, 1-Bank Module
(16 pcs of 16 M
×
4 components)
PC100 SDRAM
E0009H10 (1st edition)
(Previous ADE-203-1153A (Z))
Jan. 19, 2001
The HB52RD168GB is a 16M
×
64
×
1 bank Synchronous Dynamic RAM Micro Dual In-line Memory Module
(Micro DIMM), mounted 16 pieces of 64-Mbit SDRAM (HM5264405FTB) sealed in TCP package and 1 piece
of ser ia l EEP RO M (2- kbit EEP RO M) for P rese nce De te ct (P D). An outline of the produc t is 144-pin Zig Za g
Dua l tabs socke t type compa ct and thin pac kage . The ref ore, it make s high density mounting possible without
surf ace mount tec hnology. It provide s common data inputs and outputs. De coupling ca pac itor s ar e mounted
beside TCP on the module board.
Note: Do not push the cover or drop the modules in order to protect from mechanical defects, which would be
electrical defects.
•
144-pin Zig Zag Dual tabs socket type
Outline: 38.00 mm (Length)
×
30.00 mm (Height)
×
3.80 mm (Thickness)
Lead pitch: 0.50 mm
•
3.3 V power supply
•
Clock frequency: 100 MHz (max)
•
LVTTL interface
•
Data bus width:
×
64 Non parity
•
Single pulsed
RAS
•
4 Banks can operates simultaneously and independently
•
Burst read/write operation and burst read/single write operation capability
•
Programmable burst length : 1/2/4/8/full page
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
L
o
Pr
du
ct
HB52RD168GB-F
•
2 variations of burst sequence
Sequential (BL = 1/2/4/8/full page)
Interleave (BL = 1/2/4/8)
•
Programmable
CE
latency : 2/3 (HB52RD168GB-A6F/A6FL)
: 3 (HB52RD168GB-B6F/B6FL)
•
Byte control by DQMB
•
Refresh cycles: 4096 refresh cycles/64 ms
•
2 variations of refresh
Auto refresh
Self refresh
•
Low self refresh current: HB52RD168GB-A6FL/B6FL (L-version)
•
Full page burst length capability
Sequential burst
Burst stop capability
EO
Ordering Information
Type No.
HB52RD168GB-A6F
HB52RD168GB-B6F
HB52RD168GB-A6FL
HB52RD168GB-B6FL
100
100
100
100
L
Frequency
MHz
MHz
MHz
MHz
1pin
2pin
o
Pr
CE
latency
Package
2/3
3
2/3
3
Front Side
143pin
144pin
Back Side
Contact pad
Gold
Micro DIMM (144-pin)
Pin Arrangement
du
ct
Data Sheet E0009H10
2
HB52RD168GB-F
Front side
Pin No.
67
69
71
Signal name Pin No.
W
139
141
143
Back side
Signal name Pin No.
V
SS
SDA
V
CC
68
70
72
Signal name Pin No.
NC
NC
NC
140
142
144
Signal name
V
SS
SCL
V
CC
EO
S0
NC
Pin Description
Pin name
A0 to A11
Function
Address input
Row address A0 to A11
Column address A0 to A9
BA1, BA0
L
A12/A13
DQ0 to DQ63
S0
RE
CE
W
DQMB0 to DQMB7
CK0/CK1
CKE0
SDA
SCL
V
CC
V
SS
NC
Bank select address
Data-input/output
Chip select
Data Sheet E0009H10
4
o
Pr
Row address asserted bank enable
Column address asserted
Write enable
Byte input/output mask
Clock input
Clock enable
Data-input/output for serial PD
Clock input for serial PD
Power supply
Ground
du
ct
No connection
HB52RD168GB-F
Serial PD Matrix*
1
EO
Byte No. Function described
0
1
2
3
4
5
6
7
8
9
Number of bytes used by
module manufacturer
Total SPD memory size
Memory type
Number of banks
Module data width
SDRAM cycle time
(highest
CE
latency)
10 ns
10
11
12
Module configuration type
Refresh rate/type
13
14
15
SDRAM width
16
17
SDRAM device attributes:
Burst lengths supported
18
19
20
21
22
SDRAM device attributes:
CE
latency
SDRAM device attributes:
W
latency
SDRAM device attributes:
General
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
0
1
1
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
80
08
04
0C
0A
01
40
00
01
A0
128
256 byte
SDRAM
12
10
1
64
0 (+)
LVTTL
CL = 3
Number of row addresses bits 0
Number of c olumn address es bit s 0
0
0
Module data width (continued) 0
Module interface signal levels
0
SDRAM access from Clock
(highest
CE
latency)
6 ns
Error checking SDRAM width
0
SDRAM device attributes:
minimum clock delay for back-
to-back random column
addresses
1
0
SDRAM device attributes:
number of banks on SDRAM
device
SDRAM device attributes:
S
latency
SDRAM module attributes
L
1
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
60
CL = 3
Data Sheet E0009H10
5
o
Pr
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
1
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
1
1
0
0
0
1
0
1
1
0
0
00
80
Non parity
Normal
(15.625 µs)
Self refresh
16M
×
4
—
1 CLK
04
00
01
du
8F
04
4
06
01
01
2, 3
0
0
00
0E
1, 2, 4, 8, full
page
ct
Unbuffer
V
CC
± 10%