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• Organization: 1,048,576 words × 4 bits
• High speed
- 60 ns RAS access time
- 25 ns hyper page cycle time
- 17 ns CAS access time
• 1024 refresh cycles, 16 ms refresh interval
- RAS-only or CAS-before-RAS refresh
• Low power consumption
- Active: 385 mW max
- Standby: 5.5 mW max, CMOS I/O
• Read-modify-write
• TTL-compatible, three-state I/O
• JEDEC standard package and pinout
- 300 mil, 26/20-pin SOJ
• 5V power supply
• Extended data out
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SOJ
I/O0
I/O1
WE
RAS
A9
1
2
3
4
5
26
25
24
23
22
GND
I/O3
I/O2
CAS
OE
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Pin(s)
A0 to A9
RAS
I/O0 to I/O3
OE
WE
18
17
16
15
14
A8
A7
A6
A5
A4
Description
Address inputs
Row address strobe
Input/output
Output enable
Write enable
Column address strobe
Power
Ground
AS4C14405
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A0
A1
A2
A3
V
CC
9
10
11
12
13
CAS
V
CC
GND
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Symbol
Maximum RAS access time
Maximum column address access time
Maximum CAS access time
Maximum output enable (OE) access time
Minimum read or write cycle time
Minimum hyper page mode cycle time
Maximum operating current
Maximum CMOS standby current
t
RAC
t
AA
t
CAC
t
OEA
t
RC
t
HPC
I
CC1
I
CC5
AS4C14405-60
60
30
17
15
110
25
70
1.0
Unit
ns
ns
ns
ns
ns
ns
mA
mA
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Copyright ©1998 Alliance Semiconductor. All rights reserved.
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The AS4C14405 is a high performance CMOS Dynamic Random Access Memory organized as 1,048,576 words × 4 bits. The AS4C14405 is
fabricated with advanced CMOS technology and designed with innovative design techniques resulting in a high speed component required
by high performance systems.
The AS4C14405 features a high speed page mode operation in which high speed read, write and read-write are performed on any of the
1024
×
4 bits defined by the column address. The asynchronous column address uses an extremely short row address capture time to ease
the system level timing constraints associated with multiplexed addressing. Very fast CAS to output access time eases system design. In
contrast to ‘fast page mode’ devices, data remains active on outputs after CAS is de-asserted high, giving system logic more time to latch the
data.
Refresh on the 1024 address combinations of A0 to A9 during a 16 ms period is accomplished by performing any of the following:
• RAS-only refresh cycles
• Hidden refresh cycles
• CAS-before-RAS refresh cycles
• Normal read or write cycles
The AS4C14405 is available in JEDEC standard 20/26-pin plastic SOJ packages. System level features include single power supply of 5.0
±
0.5V tolerance and direct interface with TTL logic families.
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Vcc
Column decoder
Sense amp
Data
I/O
buffer
I/O3
I/O2
I/O1
I/O0
Refresh
controllers
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
'5$0
GND
OE
Address buffers
Row decoder
1024 × 1024 × 4
Array
(4,194,304)
RAS
RAS clock
generator
CAS
CAS clock
generator
WE
WE clock
generator
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Parameter
Supply voltage
Input voltage
Ambient operating temperature
†
Symbol
AS4C14405
AS4C14405
V
CC
GND
V
IH
V
IL
T
A
Min
4.5
0.0
2.4
–0.5
†
0
Nominal
5.0
0.0
–
–
Max
5.5
0.0
V
CC
0.8
70
Unit
V
V
V
V
°C
V
IL
min -3.0V for pulse widths less than 5 ns.
Recommended operating conditions apply throughout this document unlesss otherwise specified.
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Parameter
Input voltage
Input voltage (I/Os)
Power supply voltage
Storage temperature (plastic)
Soldering temperature × time
Power dissipation
Short circuit output current
Symbol
V
in
V
I/O
V
CC
T
STG
T
SOLDER
P
D
I
out
Min
-1.0
-1.0
-1.0
-55
–
–
–
Max
+7.0
V
CC
+ 0.5
+7.0
+150
260 × 10
1
50
Unit
V
V
V
°C
o
C × sec
W
mA
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-60
Parameter
Input leakage current
Output leakage current
Operating power supply current
TTL standby power supply current
Average power supply current,
RAS refresh mode or CBR
Hyper page mode average power
supply current
CMOS standby power supply current
Output voltage
CAS before RAS refresh current
Symbol
I
IL
I
OL
I
CC1
I
CC2
I
CC3
I
CC4
I
CC5
V
OH
V
OL
I
CC6
Test conditions
0V
≤
V
in
≤
+5.5V,
Pins not under test = 0V
D
OUT
disabled, 0V
≤
V
out
≤
+5.5V
RAS, CAS, Address cycling; t
RC
=min
RAS = CAS
≥
V
IH
RAS cycling, CAS
≥
V
IH
,
t
RC
= min of RAS low after CAS low
RAS = V
IL
, CAS,
address cycling: t
HPC
= min
RAS = CAS = V
CC
- 0.2V
I
OUT
= -5.0 mA
I
OUT
= 4.2 mA
RAS, CAS cycling, t
RC
= min
Min
-2
-10
–
–
–
–
–
2.4
–
–
Max
+2
+10
70
2.0
70
90
1.0
–
0.4
70
Unit
µA
µA
mA
mA
mA
mA
mA
V
V
mA
1
1, 2
1,2
Notes
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Symbol
t
RC
t
RP
t
RAS
t
CAS
t
RCD
t
RAD
t
RSH
t
CSH
t
CRP
t
ASR
t
RAH
t
T
t
REF
t
CP
Parameter
Random read or write cycle time
RAS precharge time
RAS pulse width
CAS pulse width
RAS to CAS delay time
RAS to column address delay time
CAS to RAS hold time
RAS to CAS hold time
CAS to RAS precharge time
Row address setup time
Row address hold time
Transition time (rise and fall)
Refresh period
CAS precharge time
Column address to RAS lead time
Column address setup time
Column address hold time
Min
110
40
60
13
20
15
15
60
5
0
10
2
–
10
30
0
10
Max
–
–
10K
10K
45
30
–
–
–
–
–
50
16
–
–
–
–
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns
4,5
3
6
7
Notes
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t
RAL
t
ASC
t
CAH
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Symbol
t
RAC
t
CAC
t
AA
t
RCS
t
RCH
t
RRH
Parameter
Access time from RAS
Access time from CAS
Access time from address
Read command setup time
Read command hold time to CAS
Read command hold time to RAS
Min
–
–
–
0
0
0
Max
60
17
30
–
–
–
Unit
ns
ns
ns
ns
ns
ns
9
9
Notes
6
6,13
7,13
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Symbol
t
WCS
t
WCH
t
WP
t
RWL
t
CWL
t
DS
t
DH
Parameter
Write command setup time
Write command hold time
Write command pulse width
Write command to RAS lead time
Write command to CAS lead time
Data-in setup time
Data-in hold time
Min
0
10
10
15
15
0
10
Max
–
–
–
–
–
–
–
Unit
ns
ns
ns
ns
ns
ns
ns
12
12
Notes
11
11
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Symbol
t
RWC
t
RWD
t
CWD
t
AWD
Parameter
Read-write cycle time
RAS to WE delay time
CAS to WE delay time
Column address to WE delay time
Min
135
77
35
47
Max
–
–
–
–
Unit
ns
ns
ns
ns
11
11
11
Notes
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Symbol
t
CSR
t
CHR
t
RPC
t
CPT
Parameter
CAS setup time (CAS-before-RAS)
CAS hold time (CAS-before-RAS)
RAS precharge to CAS hold time
CAS precharge time
(CBR counter test)
Min
10
10
0
10
Max
–
–
–
–
Unit
ns
ns
ns
ns
Notes
3
3
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