multiple CPU data interfaces to effectively address
both current and emerging fast Ethernet applications
when port 5 is configured to separate MAC5 with
SW5-MII/RMII and PHY5 with P5-MII/RMII interfaces.
The KSZ8895 family offers three configurations,
providing the flexibility to meet different requirements:
•
•
•
KSZ8895MQ: Five 10/100Base-T/TX transceivers,
one SW5-MII and one P5-MII interface,
KSZ8895RQ: Five 10/100Base-T/TX transceivers,
one SW5-RMII and one P5-RMII interface
KSZ8895FMQ: Three 10/100Base-T/TX
transceivers on Ports 1, 2, 5 and two 100Base-FX
transceivers on Ports 3, 4, one SW5-MII and one
P5-MII interface
All registers of MACs and PHYs units can be
managed by the SPI or the SMI interface. MIIM
registers can be accessed through the MDC/MDIO
interface. EEPROM can set all control registers for the
unmanaged mode. KSZ8895MQ/RQ/FMQ are 128-pin
PQFP packages.
Functional Diagram
Note:
SW5 indicates the MAC5 of the switch side, P5 indicates the PHY5 of the Port 5.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 •
http://www.micrel.com
March 19, 2014
Revision 1.7
Micrel, Inc.
KSZ8895MQ/RQ/FMQ
Features
Advanced Switch Features
•
•
•
•
•
•
•
•
•
•
IEEE 802.1q VLAN support for up to 128 active VLAN groups
(full-range 4096 of VLAN IDs).
Static MAC table supports up to 32 entries.
VLAN ID tag/untag options, per port basis
IEEE 802.1p/q tag insertion or removal on a per port basis
based on ingress port (egress).
Programmable rate limiting at the ingress and egress on a per
port basis.
Jitter-free per packet based rate limiting support.
Broadcast storm protection with percentage control (global
and per port basis).
IEEE 802.1d rapid spanning tree protocol RSTP support.
Tail tag mode (1 byte added before FCS) support at Port 5 to
inform the processor which ingress port receives the packet.
1.4Gbps high-performance memory bandwidth and shared
memory-based switch fabric with fully
non-blocking configuration.
Dual MII with MAC5 and PHY5 on port 5, SW5-MII/RMII for
MAC 5 and P5-MII/RMII for PHY 5.
Enable/Disable option for huge frame size up to 2000 Bytes
per frame.
IGMP v1/v2 snooping (Ipv4) support for multicast packet
filtering.
IPv4/IPv6 QoS support.
Support unknown unicast/multicast address and unknown VID
packet filtering.
•
•
•
•
•
•
•
•
On-chip 64Kbyte memory for frame buffering (not shared with
1K unicast address table).
Full duplex IEEE 802.3x flow control (PAUSE) with force
mode option.
Half-duplex back pressure flow control.
HP Auto MDI/MDI-X and IEEE Auto crossover support.
SW-MII interface supports both MAC mode and PHY mode.
7-wire serial network interface (SNI) support for legacy MAC.
Per port LED Indicators for link, activity, and 10/100 speed.
Register port status support for link, activity, full/half duplex
and 10/100 speed.
On-chip terminations and internal biasing technology for cost
down and lowest power consumption.
Port mirroring/monitoring/sniffing: ingress and/or egress traffic
to any port or MII.
MIB counters for fully compliant statistics gathering 34 MIB
counters per port.
Loop-back support for MAC, PHY and remote diagnostic of
failure.
•
Switch Monitoring Features
•
•
•
•
•
•
•
•
•
Interrupt for the link change on any ports
.
Low Power Dissipation
•
•
•
•
•
•
Full-chip hardware power-down.
Full-chip software power-down and per port software power
down.
Energy-detect mode support < 100mW full chip-power
consumption when all ports have no activity.
Very low full chip power consumption (<0.5W), without extra
power consumption on transformers.
Dynamic clock tree shutdown feature.
Voltages: Single 3.3V supply with 3.3V VDDIO and Internal
1.2V LDO controller enabled, or external 1.2V LDO solution.
–
–
–
•
•
•
Analog VDDAT 3.3V only.
VDDIO support 3.3V, 2.5V and 1.8V.
Low 1.2V core power .
•
Self-address filtering.
Comprehensive Configuration Register Access
•
•
•
•
Serial management interface (MDC/MDIO) to all PHYs
registers and SMI interface (MDC/MDIO) to all registers.
High speed SPI (up to 25MHz) and I C master Interface to all
internal registers.
I/0 pins strapping and EEPROM to program selective
registers in unmanaged switch mode.
Control registers configurable on the fly (port-priority,
802.1p/d/q, AN).
Per port, 802.1p and DiffServ-based.
1/2/4-queue QoS prioritization selection.
Programmable weighted fair queuing for ratio control.
Re-mapping of 802.1p priority field per port basis.
New generation switch with five MACs and five PHYs with
fully compliant with IEEE 802.3u standard.
PHYs designed
technology.
with
patented
enhanced
mixed-signal
2
0.13µm CMOS technology.
Commercial temperature range: 0°C to +70°C.
Industrial Temperature Range: -40°C to +85°C.
Available in 128-pin PQFP lead-free package.
VoIP phone
Set-top/game box
Automotive
Industrial control
IPTV POF
SOHO residential gateway
Broadband gateway/firewall/VPN
Integrated DSL/cable modem
Wireless LAN access point + gateway
Standalone 10/100 switch
QoS/CoS Packet Prioritization Support
•
•
•
•
•
•
•
•
•
•
•
•
•
Applications
•
•
•
•
Integrated Five-Port 10/100 Ethernet Switch
Non-blocking switch fabric assures fast packet delivery by
utilizing a 1K MAC address lookup table and a store-and-
forward architecture.
•
March 19, 2014
2
Revision 1.7
Micrel, Inc.
KSZ8895MQ/RQ/FMQ
Ordering Information
Part Number
KSZ8895MQ
KSZ8895MQI
KSZ8895RQ
KSZ8895RQI
KSZ8895FMQ
KSZ8895FMQI
KSZ8895MQ-EVAL
KSZ8895RQ-EVAL
KSZ8895FMQ-Eval
Note:
1. Please consult sales for the availability
Temperature Range
0°C to 70°C
−40°C
to +85°C
0°C to 70°C
−40°C
to +85°C
0°C to 70°C
−40°C
to +85°C
Package
128-Pin PQFP
128-Pin PQFP
128-Pin PQFP
128-Pin PQFP
128-Pin PQFP
128-Pin PQFP
Lead Finish/Grade
Pb-Free/Commercial
Pb-Free/Industrial
Pb-Free/Commercial
Pb-Free/Industrial
Pb-Free/Commercial
Pb-Free/Industrial
Evaluation Board for KSZ8895MQ
Evaluation Board for KSZ8895RQ
Evaluation Board for KSZ8895FMQ
Revision History
Revision
1.0
1.1
1.2
1.3
1.4
Date
09/13/10
11/16/10
01/20/11
03/18/11
08/30/11
Description
Initial document created
Remove TMQ part
Update the ordering information and some data.
Update the register number, descriptions and correct typo error.
Correct typo error for package information and update some
descriptions for SMI mode and IGMP and update register default
values, pins type and some parameters.
Update descriptions for Pin, register 1 chip ID, port register,
VLAN table and I2C master. Update the equation in the
broadcast storm protection section. Update table of strap-in pins.
Update the ordering information for RQ parts.
Update the ordering information for FMQ parts available. Correct
typos. Update the operation rating to ±5% and TTL min/max I/O
voltage in different VDDIO. Add register 165 for FMQ part with
fiber mode. Update a note for pin 125 descriptions.
Change I/O from TTL to CMOS. Update SPI description from
127 to 255 for access registers. Update Register 6 offset. Update
register offset mapping index. Correct typos. Updates timing data
for MII PHY mode. Update the table of tail tag rules. Update
description for Register 1 bits [7:4]. Update Table 8 from bit
[57:55] to bit [58:56]. Update the port register control 2 bit [6]
description (bits [20:16] change to bits [11:7]). Update Table 33.
Add evaluation Board in ordering information table. Update a
note for pin 126 descriptions.
1.5
02/24/12
1.6
11/28/12
1.7
03/12/14
March 12, 2014
3
Revision 1.7
Micrel, Inc.
KSZ8895MQ/RQ/FMQ
Contents
System Level Applications ...........................................................................................................................................13
Pin for Strap-In Options ................................................................................................................................................23
100BASE-FX Signal Detection ...................................................................................................................................27
100BASE-FX Far End Fault ........................................................................................................................................27
MDI/MDI-X Auto Crossover ........................................................................................................................................27
Functional Overview: Power Management .................................................................................................................31
Normal Operation Mode .............................................................................................................................................31
Energy Detect Mode ...................................................................................................................................................32
Soft Power Down Mode ..............................................................................................................................................32
Power Saving Mode ....................................................................................................................................................32
Port-based Power Down Mode ...................................................................................................................................32
Media Access Controller (MAC) Operation ................................................................................................................33
Inter-Packet Gap (IPG) ...........................................................................................................................................34
Late Collision ..........................................................................................................................................................34
Flow Control ............................................................................................................................................................34
Half-Duplex Back Pressure ....................................................................................................................................37
MII Interface Operation ...............................................................................................................................................38
March 12, 2014
4
Revision 1.7
Micrel, Inc.
KSZ8895MQ/RQ/FMQ
Port 5 PHY 5 P5-MII/RMII Interface............................................................................................................................38
Port 5 MAC 5 SW5-MII Interface for the KSZ8895MQ/FMQ ......................................................................................39
Port 5 MAC 5 Switch SW5-RMII Interface for the KSZ8895RQ .................................................................................40
QoS Priority Support ...................................................................................................................................................42
Spanning Tree Support ...............................................................................................................................................43
Rapid Spanning Tree Support ....................................................................................................................................44
IGMP Support .............................................................................................................................................................46
Port Mirroring Support ................................................................................................................................................46
VLAN Support .............................................................................................................................................................46
Rate Limiting Support .................................................................................................................................................47
Transmit Queue Ratio Programming ......................................................................................................................48
Filtering for Self-Address, Unknown Unicast/Multicast Address and Unknown VID Packet/IP Multicast ..................48
I C Master Serial Bus Configuration .......................................................................................................................48
SPI Slave Serial Bus Configuration ........................................................................................................................49
MII Management Interface (MIIM) ..........................................................................................................................52
Serial Management Interface (SMI) ........................................................................................................................52
Global Registers .........................................................................................................................................................56
Register 2 (0x02): Global Control 0 ........................................................................................................................56
Register 3 (0x03): Global Control 1 ........................................................................................................................57
Register 4 (0x04): Global Control 2 ........................................................................................................................58
Register 5 (0x05): Global Control 3 ........................................................................................................................59
Register 6 (0x06): Global Control 4 ........................................................................................................................60
Register 7 (0x07): Global Control 5 ........................................................................................................................61
Register 8 (0x08): Global Control 6 ........................................................................................................................61
Register 9 (0x09): Global Control 7 ........................................................................................................................61
Register 10 (0x0A): Global Control 8......................................................................................................................62
Register 11 (0x0B): Global Control 9......................................................................................................................62
Register 12 (0x0C): Global Control 10 ...................................................................................................................63
Register 13 (0x0D): Global Control 11 ...................................................................................................................63
Register 14 (0x0E): Power Down Management Control 1 .....................................................................................63
Register 15 (0x0F): Power Down Management Control 2......................................................................................64
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