EDI88130LPS45TI datasheet, PDF

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EDI88130LPS45TI: DescriptionStandard SRAM, 128KX8, 45ns, CMOS, CDIP32, 0.400 INCH, SIDE BRAZED, CERAMIC, DIP-32; Categorystorage storage; File Size500KB，9 Pages; ManufacturerWhite Electronic Designs Corporation; Websitehttp://www.wedc.com/

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EDI88130LPS45TI Overview

Standard SRAM, 128KX8, 45ns, CMOS, CDIP32, 0.400 INCH, SIDE BRAZED, CERAMIC, DIP-32

EDI88130LPS45TI Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	White Electronic Designs Corporation
package instruction	0.400 INCH, SIDE BRAZED, CERAMIC, DIP-32
Reach Compliance Code	unknown
Maximum access time	45 ns
Other features	BATTERY BACKUP OPERATION
I/O type	COMMON
JESD-30 code	R-CDIP-T32
length	40.64 mm
memory density	1048576 bit
Memory IC Type	STANDARD SRAM
memory width	8
Number of functions	1
Number of terminals	32
word count	131072 words
character code	128000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	128KX8
Output characteristics	3-STATE
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	DIP
Encapsulate equivalent code	DIP32,.4
Package shape	RECTANGULAR
Package form	IN-LINE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5 V
Certification status	Not Qualified
Maximum seat height	3.937 mm
Maximum standby current	0.002 A
Minimum standby current	2 V
Maximum slew rate	0.2 mA
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	10.16 mm
Base Number Matches	1

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White Electronic Designs

128Kx8 Monolithic SRAM, SMD 5962-89598

FEATURES

Access Times of 15*, 17, 20, 25, 35, 45, 55ns

Battery Back-up Operation

• 2V Data Retention (EDI88130LPS)

CS1#, CS2 & OE# Functions for Bus Control

Inputs and Outputs Directly TTL Compatible

Organized as 128Kx8

Commercial, Industrial and Military Temperature

Ranges

Thru-hole and Surface Mount Packages JEDEC

Pinout

• 32 pin Sidebrazed Ceramic DIP, 400 mil

(Package 102)

• 32 pin Sidebrazed Ceramic DIP, 600 mil

(Package 9)

• 32 lead Ceramic SOJ (Package 140)

• 32 pad Ceramic Quad LCC (Package 12)

• 32 pad Ceramic LCC (Package 141)

• 32 lead Ceramic Flatpack (Package 142)

EDI88130CS

Single +5V (±10%) Supply OperationThe

EDI88130CS is a high speed, high performance,

128Kx8 bits monolithic Static RAM.

An additional chip enable line provides system memory

security during power down in non-battery backed up

systems and memory banking in high speed battery

backed systems where large multiple pages of memory

are required.

The EDI88130CS has eight bi-directional input-output lines

to provide simultaneous access to all bits in a word.

A low power version, EDI88130LPS, offers a 2V data

retention function for battery back-up applications.

Military product is available compliant to MIL-PRF-

38535.

* 15ns access time is advanced information, contact factory for availability.

FIGURE 1 – PIN CONFIGURATION

32 DIP

32 SOJ

32 CLCC

32 FLATPACK

TOP VIEW

A16

A14

A12

I/O0

I/O1

I/O2

A15

CS2#

WE#

A13

A11

OE#

A10

CS1#

I/O7

I/O6

I/O5

I/O4

I/O3

32 QUAD LCC

TOP VIEW

A12

A14

A16

A15

CS2

PIN DESCRIPTION

I/O0-7

A0-16

WE#

CS1#, CS2

OE#

Data Input/Output

Address Inputs

Write Enable

Chip Select

Output Enable

Power Supply

Ground

Not Connected

I/O0

WE#

A13

A11

OE#

A10

CS1#

I/O7

Block Diagram

Memory Array

I/O1

I/O2

I/O3

I/O4

I/O5

I/O6

A0-16

Address

Buffer

Address

Decoder

I/O

Circuits

I/O0-7

WE#

CS1#

CS2

OE#

White Electronic Designs Corp. reserves the right to change products or speciﬁcations without notice.

March 2002

Rev. 11

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

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