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72T2098L4BB

Description
PBGA-208, Tray
Categorystorage    storage   
File Size505KB,51 Pages
ManufacturerIDT (Integrated Device Technology)
Download Datasheet Parametric View All

72T2098L4BB Overview

PBGA-208, Tray

72T2098L4BB Parametric

Parameter NameAttribute value
Brand NameIntegrated Device Technology
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerIDT (Integrated Device Technology)
Parts packaging codePBGA
package instruction17 X 17 MM, 1 MM PITCH, PLASTIC, BGA-208
Contacts208
Manufacturer packaging codeBB208
Reach Compliance Codenot_compliant
ECCN codeEAR99
Maximum access time3.2 ns
Other featuresALTERNATIVE MEMORY WIDTH 10
Spare memory width10
Maximum clock frequency (fCLK)250 MHz
period time4 ns
JESD-30 codeS-PBGA-B208
JESD-609 codee0
length17 mm
memory density655360 bit
Memory IC TypeOTHER FIFO
memory width20
Humidity sensitivity level3
Number of functions1
Number of terminals208
word count32768 words
character code32000
Operating modeSYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize32KX20
ExportableYES
Package body materialPLASTIC/EPOXY
encapsulated codeBGA
Encapsulate equivalent codeBGA208,16X16,40
Package shapeSQUARE
Package formGRID ARRAY
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)225
power supply1.5/2.5,2.5 V
Certification statusNot Qualified
Maximum seat height1.97 mm
Maximum standby current0.05 A
Maximum slew rate0.06 mA
Maximum supply voltage (Vsup)2.625 V
Minimum supply voltage (Vsup)2.375 V
Nominal supply voltage (Vsup)2.5 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn63Pb37)
Terminal formBALL
Terminal pitch1 mm
Terminal locationBOTTOM
Maximum time at peak reflow temperatureNOT SPECIFIED
width17 mm
Base Number Matches1
2.5 VOLT HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATION
32,768 x 20/65,536 x 10, 65,536 x 20/131,072 x 10
131,072 x 20/262,144 x 10, 262,144 x 20/524,288 x 10
IDT72T2098, IDT72T20108
IDT72T20118, IDT72T20128
FEATURES
Choose among the following memory organizations:
IDT72T2098
32,768 x 20/65,536 x 10
IDT72T20108
65,536 x 20/131,072 x 10
IDT72T20118
131,072 x 20/262,144 x 10
IDT72T20128
262,144 x 20/524,288 x 10
Up to 250MHz operating frequency or 5Gbps throughput in SDR mode
Up to 110MHz operating frequency or 5Gbps throughput in DDR mode
Users selectable input port to output port data rates, 500Mb/s
Data Rate
-DDR to DDR
-DDR to SDR
-SDR to DDR
-SDR to SDR
User selectable HSTL or LVTTL I/Os
Read Enable & Read Clock Echo outputs aid high speed operation
2.5V LVTTL or 1.8V, 1.5V HSTL Port Selectable Input/Ouput voltage
3.3V Input tolerant
Mark & Retransmit, resets read pointer to user marked position
Write Chip Select (WCS) input enables/disables Write
Operations
Read Chip Select (RCS) synchronous to RCLK
Programmable Almost-Empty and Almost-Full flags, each flag
can default to one of four preselected offsets
Dedicated serial clock input for serial programming of flag offsets
User selectable input and output port bus sizing
-x20 in to x20 out
-x20 in to x10 out
-x10 in to x20 out
-x10 in to x10 out
Auto power down minimizes standby power consumption
Master Reset clears entire FIFO
Partial Reset clears data, but retains programmable settings
Empty and Full flags signal FIFO status
Select IDT Standard timing (using
EF
and
FF
flags) or First
Word Fall Through timing (using
OR
and
IR
flags)
Output enable puts data outputs into High-Impedance state
JTAG port, provided for Boundary Scan function
208 Ball Grid array (PBGA), 17mm x 17mm, 1mm pitch
Easily expandable in depth and width
Independent Read and Write Clocks (permit reading and writing
simultaneously)
High-performance submicron CMOS technology
°
°
Industrial temperature range (-40°C to +85°C) is available
FUNCTIONAL BLOCK DIAGRAM
D
0
-D
n
(x20, x10)
WEN
WCS
WCLK
SREN SEN
SCLK
WSDR
INPUT REGISTER
OFFSET REGISTER
SI
SO
FF/IR
PAF
EF/OR
PAE
FWFT
FSEL0
FSEL1
WRITE CONTROL
LOGIC
FLAG
LOGIC
RAM ARRAY
32,768 x 20 or 65,536 x 10
65,536 x 20 or 131,072 x 10
131,072 x 20 or 262,144 x 10
262,144 x 20 or 524,288 x 10
WRITE POINTER
READ POINTER
IW
OW
MRS
PRS
TCK
TRST
TMS
TDO
TDI
Vref
HSTL
BUS
CONFIGURATION
RESET
LOGIC
OUTPUT REGISTER
READ
CONTROL
LOGIC
RT
MARK
RSDR
JTAG CONTROL
(BOUNDARY SCAN)
RCLK
REN
RCS
HSTL I/0
CONTROL
OE
EREN
5996 drw01
Q
0
-Q
n
(x20, x10)
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. The TeraSync is a trademark of Integrated Device Technology, Inc.
ERCLK
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
2004 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
SEPTEMBER 2004
DSC-5996/9

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