CXK77P36E160GB-4AF datasheet, PDF

Datasheet> All Categories > storage> storage> CXK77P36E160GB-4AF

CXK77P36E160GB-4AF: DescriptionStandard SRAM, 512KX36, 3.8ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, BGA-119; Categorystorage storage; File Size257KB，25 Pages; ManufacturerSONY; Websitehttp://www.sony.co.jp

Download Datasheet Parametric View All

CXK77P36E160GB-4AF Overview

Standard SRAM, 512KX36, 3.8ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, BGA-119

CXK77P36E160GB-4AF Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	SONY
Parts packaging code	BGA
package instruction	BGA, BGA119,7X17,50
Contacts	119
Reach Compliance Code	unknown
ECCN code	3A991.B.2.A
Maximum access time	3.8 ns
Spare memory width	36
Maximum clock frequency (fCLK)	250 MHz
I/O type	COMMON
JESD-30 code	R-PBGA-B119
JESD-609 code	e0
length	22 mm
memory density	18874368 bit
Memory IC Type	STANDARD SRAM
memory width	36
Number of functions	1
Number of terminals	119
word count	524288 words
character code	512000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature
organize	512KX36
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Encapsulate equivalent code	BGA119,7X17,50
Package shape	RECTANGULAR
Package form	GRID ARRAY
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	240
power supply	1.9,3.3 V
Certification status	Not Qualified
Maximum seat height	2.5 mm
Maximum standby current	0.25 A
Minimum standby current	3.14 V
Maximum slew rate	0.75 mA
Maximum supply voltage (Vsup)	3.47 V
Minimum supply voltage (Vsup)	3.13 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	OTHER
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	10
width	14 mm
Base Number Matches	1

Preview

Download Datasheet

View All

SONY

CXK77P36E160GB / CXK77P18E160GB

4/42/43/44

Preliminary

16Mb LW R-L HSTL High Speed Synchronous SRAMs (512K x 36 or 1M x 18)

8Mb LW R-L w/ EC HSTL High Speed Synchronous SRAMs (256K x 36 or 512K x 18)

Description

The CXK77P36E160GB (organized as 524,288 words by 36 bits) and the CXK77P18E160GB (organized as 1,048,576 words

by 18 bits) are high speed CMOS synchronous static RAMs with common I/O pins. These synchronous SRAMs integrate input

registers, high speed RAM, output latches, and a one-deep write buffer onto a single monolithic IC. Register - Latch (R-L) read

operations and Late Write (LW) write operations are supported, providing a high-performance user interface.

Two distinct R-L modes of operation are supported, selectable via the M2 mode pin. When M2 is “high”, these devices function

as conventional 16Mb R-L SRAMs, and pin 2B functions as a conventional SA address input. When M2 is “low”, these devices

function as Error-Correcting (EC) 8Mb R-L SRAMs, and pin 2B is ignored.

When Error-Correcting 8Mb R-L mode is selected, the SRAM is divided into two banks internally - a “primary” bank and a

“secondary” bank. During write operations, input data is ultimately written to both banks internally (through one stage of write

pipelining). During read operations, data is read from both banks internally, and each byte of primary bank data is individually

parity-checked. If the parity of a particular byte of primary data is correct (that is, “odd”), it is driven valid externally. If the

parity of a particular byte of primary data is incorrect (that is, “even”), it is discarded, and the corresponding byte of secondary

bank data is driven valid externally. Primary / secondary bank data selection is performed on each data byte independently.

Data read from the secondary bank is NOT parity-checked.

Data read from the write buffer is NOT parity-checked.

All address and control input signals except ZZ (Sleep Mode) are registered on the rising edge of K (Input Clock).

During read operations, output data is driven valid from the falling edge of K, one half clock cycle after the address is registered.

During write operations, input data is registered on the rising edge of K, one full clock cycle after the address is registered.

The output drivers are series terminated, and the output impedance is programmable through an external impedance matching

resistor RQ. By connecting RQ between ZQ and V

, the output impedance of all DQ pins can be precisely controlled.

Sleep (power down) mode control is provided through the asynchronous ZZ input. 250 MHz operation is obtained from a single

3.3V power supply. JTAG boundary scan interface is provided using a subset of IEEE standard 1149.1 protocol.

Features

•

4 Speed Bins

-4 (-4A) (-4B)

-42 (-42A) (-42B)

-43 (-43A) (-43B)

-44

Cycle Time / Access Time

4.0ns / 3.9ns (3.8ns) (3.7ns)

4.2ns / 4.2ns (4.1ns) (4.0ns)

4.3ns / 4.5ns (4.4ns) (4.3ns)

4.4ns / 4.7ns

•

Single 3.3V power supply (V

): 3.3V

Dedicated output supply voltage (V

DDQ

): 1.9V typical

HSTL-compatible I/O interface with dedicated input reference voltage (V

REF

): 0.85V typical

Late Write (LW) write operations

Conventional 16Mb or Error-Correcting (EC) 8Mb mode of operation, selectable via dedicated mode pin (M2)

Full read/write coherency

Byte Write capability

One cycle deselect

Differential input clocks (K/K)

Programmable impedance output drivers

Sleep (power down) mode via dedicated mode pin (ZZ)

JTAG boundary scan (subset of IEEE standard 1149.1)

119 pin (7x17), 1.27mm pitch, 14mm x 22mm Ball Grid Array (BGA) package

16Mb LW R-L and 8Mb LW R-L w/ EC, rev 1.1

1 / 25

March 2, 2001

Recommended Resources

Current doubler rectifier DC/DC converter circuit

SH-811 Holiday Lights ASIC

Modulator circuit for test signal generator

Power supply voltage polarity conversion circuit composed of gate circuit

Output 80Vp-p suspended load amplifier circuit

Leakage indication circuit

Application of high-torque micro-displacement platform based on piezoelectric stack in performance testing of power amplifier: Experiment name: Research on high-torque micro-displacement platform based on piezoelectric stack Research direction: Performance testing of micro-displacement platforms Experimental content: In order...; aigtek01 LED Zone

Request a free ZVS buck-boost evaluation board!: [font=微软雅黑][size=3]PI37xx is a series of high efficiency, wide input range DC-DC ZVS buck-boost regulators that integrate a ZVS controller, power switch and supporting components in a system-in-packag...; eric_wang Power technology

bq30z50/55 senc file export configuration process: 1. Check that the Data Flash content is configured correctly and ensure that it is written.Operation:a. When modifying the Data Flash content, you can directly click the parameter to be modified. When...; qwqwqw2088 Analogue and Mixed Signal

Three-cell lithium battery charging management IC-VAS5176 charging current test: [i=s]This post was last edited by yaohongxia0903 on 2019-8-1 22:14[/i]VAS5176 is a 8.5V-24V input, highly integrated switch-type lithium-ion/polymer battery charging chip that regulates 2A charging cu...; yaohongxia0903 Power technology

USB TYPE C interface problem urgent help: I have used USB3300 to drive USB in other products before, and there was no problem. Recently, a project changed the USB interface to TYPE C, rewired, and soldered 3 boards. All of them had the same p...; olive888 Analog electronics

Notice on the extension of ON Semiconductor and Avnet IoT Innovation Design Competition: Notice on the extension of ON Semiconductor and Avnet IoT Innovation Design CompetitionDear contestants:We regret to inform you that the 2020-2021 ON Semiconductor and Avnet IoT Innovation Design Comp...; EEWORLD社区 onsemi and Avnet IoT Innovation Design Competition

Shortcut: E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF EG EH EI EJ EK EL EM EN EO EP EQ ER ES ET EU EV EW EX EY EZ F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF FG FH FI FJ FK FL FM FN FO FP FQ FR FS FT FU FV FW FX FY FZ G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 GA GB GC GD GE GF GG GH GI GJ GK GL GM GN GO GP GQ GR GS GT GU GV GW GX GZ H0 H1 H2 H3 H4 H5 H6 H7 H8 HA HB HC HD HE HF HG HH HI HJ HK HL HM HN HO HP HQ HR HS HT HU HV HW HX HY HZ I1 I2 I3 I4 I5 I6 I7 IA IB IC ID IE IF IG IH II IK IL IM IN IO IP IQ IR IS IT IU IV IW IX J0 J1 J2 J6 J7 JA JB JC JD JE JF JG JH JJ JK JL JM JN JP JQ JR JS JT JV JW JX JZ K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 KA KB KC KD KE KF KG KH KI KJ KK KL KM KN KO KP KQ KR KS KT KU KV KW KX KY KZ

Popular Components