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ASM3P622S00BG-08-TT

Description
Clock Generator, 20MHz, CMOS, PDSO8, 4.40 MM, LEAD FREE, TSSOP-8
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size678KB,15 Pages
ManufacturerPulseCore Semiconductor Corporation
Download Datasheet Parametric View All

ASM3P622S00BG-08-TT Overview

Clock Generator, 20MHz, CMOS, PDSO8, 4.40 MM, LEAD FREE, TSSOP-8

ASM3P622S00BG-08-TT Parametric

Parameter NameAttribute value
MakerPulseCore Semiconductor Corporation
package instruction4.40 MM, LEAD FREE, TSSOP-8
Reach Compliance Codeunknown
JESD-30 codeR-PDSO-G8
length4.4 mm
Number of terminals8
Maximum operating temperature70 °C
Minimum operating temperature
Maximum output clock frequency20 MHz
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Master clock/crystal nominal frequency20 MHz
Certification statusNot Qualified
Maximum seat height1.1 mm
Maximum supply voltage3.6 V
Minimum supply voltage3 V
Nominal supply voltage3.3 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationDUAL
width3 mm
uPs/uCs/peripheral integrated circuit typeCLOCK GENERATOR, OTHER
Base Number Matches1
ASM3P622S00B/E
Low Frequency Timing-Safe™
Peak EMI Reduction IC
General Features
Low Frequency Clock distribution with Timing-Safe™
Peak EMI Reduction
Input frequency range: 4MHz - 20MHz
2 different Spread Selection options
Spread Spectrum can be turned ON/OFF
External Input-Output Delay Control option
Supply Voltage: 3.3V±0.3V
Commercial and Industrial temperature range
Packaging Information:
ASM3P622S00B: 8 pin SOIC, and TSSOP
ASM3P622S00E:16 pin SOIC, and TSSOP
The First True Drop-in Solution
ASM3P622S00B/E operates from a 3.3V supply and is
available in two different packages, as shown in the
ordering information table, over commercial and Industrial
temperature range.
one reference input and drives out eight low-skew Timing-
Safe™ clocks.
ASM3P622S00B/E has an SS% that selects 2 different
Deviation and associated Input-Output Skew (TSKEW).
Refer to
Spread Spectrum Control
and
Input-Output Skew
table for details.
ASM3P622S00E has a CLKOUT for adjusting the Input-
Output clock delay, depending upon the value of capacitor
connected at this pin to GND.
Functional Description
ASM3P622S00B/E is a versatile, 3.3V Zero-delay buffer
designed to distribute low frequency Timing-Safe™ clocks
with Peak EMI reduction. ASM3P622S00B is an eight-pin
version, accepts one reference input and drives out one
low-skew Timing-Safe™ clock. ASM3P622S00E accepts
Application
ASM3P622S00B/E is targeted for use in Displays and
memory interface systems.
General Block Diagram
DLY_CTRL
VDD
SS%
CLKIN
PLL
CLKOUT(s)*
(Timing-Safe™)
*For
ASM3P622S00E -
8 CLKOUTS
SSON
GND
©2010 SCILLC. All rights reserved.
JANUARY 2010 – Rev. 1
Publication Order Number:
ASM3P622S00/D
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