CAT5411
Dual Digital
Potentiometer (POT)
with 64 Taps
and SPI Interface
Description
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The CAT5411 is two digital potentiometers (POTs) integrated with
control logic and 16 bytes of NVRAM memory. Each digital POT
consists of a series of 63 resistive elements connected between two
externally accessible end points. The tap points between each resistive
element are connected to the wiper outputs with CMOS switches. A
separate 6-bit control register (WCR) independently controls the
wiper tap switches for each digital POT. Associated with each wiper
control register are four 6-bit non-volatile memory data registers (DR)
used for storing up to four wiper settings. Writing to the wiper control
register or any of the non-volatile data registers is via a SPI serial bus.
On power-up, the contents of the first data register (DR0) for each of
the two potentiometers is automatically loaded into its respective
wiper control register.
The CAT5411 can be used as a potentiometer or as a two terminal,
variable resistor. It is intended for circuit level or system level
adjustments in a wide variety of applications.
Features
TSSOP24
Y SUFFIX
CASE 948AR
SOIC−24
W SUFFIX
CASE 751BK
PIN CONNECTIONS
V
CC
R
L0
R
H0
R
W0
CS
WP
SI
A
1
R
L1
R
H1
R
W1
GND
SOIC−24 (W)
(Top View)
SI
A
1
R
L1
R
H1
R
W1
GND
NC
NC
NC
NC
SCK
HOLD
1
WP
CS
R
W0
R
H0
R
L0
V
CC
NC
NC
NC
NC
A
0
SO
CAT5411
1
NC
NC
NC
NC
A
0
SO
HOLD
SCK
NC
NC
NC
NC
Two Linear-taper Digital Potentiometers
64 Resistor Taps per Potentiometer
End to End Resistance 2.5 kW, 10 kW, 50 kW or 100 kW
Potentiometer Control and Memory Access via SPI Interface:
Mode (0, 0) and (1, 1)
Low Wiper Resistance, Typically 80
W
Nonvolatile Memory Storage for up to Four Wiper Settings for Each
Potentiometer
Automatic Recall of Saved Wiper Settings at Power Up
2.5 to 6.0 Volt Operation
Standby Current less than 1
mA
24-lead SOIC and 24-lead TSSOP
Industrial Temperature Ranges
These Devices are Pb-Free, Halogen Free/BFR Free and are RoHS
Compliant
CAT5411
TSSOP24 (Y)
(Top View)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 12 of this data sheet.
Semiconductor Components Industries, LLC, 2013
July, 2013
−
Rev. 13
1
Publication Order Number:
CAT5411/D
CAT5411
MARKING DIAGRAMS
(SOIC−24)
(TSSOP−24)
L3B
CAT5411WT
−RRYMXXXX
RLB
CAT5411YT
3YMXXX
L = Assembly Location
3 = Lead Finish
−
Matte-Tin
B = Product Revision (Fixed as “B”)
CAT = Fixed as “CAT”
5411W = Device Code
T = Temperature Range (I = Industrial)
−
= Dash
RR = Resistance
25 = 2.5 KW
10 = 10 KW
50 = 50 KW
00 = 100 KW
Y = Production Year (Last Digit)
M = Production Month (1−9, O, N, D)
XXXX = Last Four Digits of Assembly Lot Number
R = Resistance
1 = 2.5 KW
2 = 10 KW
4 = 50 KW
5 = 100 KW
L = Assembly Location
B = Product Revision (Fixed as “B”)
CAT5411Y = Device Code
T = Temperature Range (I = Industrial)
3 = Lead Finish
−
Matte-Tin
Y = Production Year (Last Digit)
M = Production Month (1−9, O, N, D)
XXX = Last Three Digits of Assembly Lot Number
R
H0
R
H1
CS
SCK
SI
SO
SPI BUS
INTERFACE
WIPER
CONTROL
REGISTERS
R
W0
R
W1
WP
A0
A1
CONTROL
LOGIC
NONVOLATILE
DATA
REGISTERS
R
L0
R
L1
Figure 1. Functional Diagram
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2
CAT5411
PIN DESCRIPTIONS
SI: Serial Input
HOLD: Hold
SI is the serial data input pin. This pin is used to input all
opcodes, byte addresses and data to be written to the
CAT5411. Input data is latched on the rising edge of the
serial clock.
SO: Serial Output
SO is the serial data output pin. This pin is used to transfer
data out of the CAT5411. During a read cycle, data is shifted
out on the falling edge of the serial clock.
SCK: Serial Clock
The HOLD pin is used to pause transmission to the
CAT5411 while in the middle of a serial sequence without
having to re-transmit entire sequence at a later time. To
pause, HOLD must be brought low while SCK is low. The
SO pin is in a high impedance state during the time the part
is paused, and transitions on the SI pins will be ignored. To
resume communication, HOLD is brought high, while SCK
is low. (HOLD should be held high any time this function is
not being used.) HOLD may be tied high directly to V
CC
or
tied to V
CC
through a resistor.
Table 1. PIN CONNECTIONS
Pin
SOIC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Pin
TSSOP
19
20
21
22
23
24
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Name
V
CC
R
L0
R
H0
R
W0
CS
WP
SI
A
1
R
L1
R
H1
R
W1
GND
NC
NC
NC
NC
SCK
HOLD
SO
A
0
NC
NC
NC
NC
Function
Supply Voltage
Low Reference Terminal
for Potentiometer 0
High Reference Terminal
for Potentiometer 0
Wiper Terminal for
Potentiometer 0
Chip Select
Write Protection
Serial Input
Device Address
Low Reference Terminal
for Potentiometer 1
High Reference Terminal
for Potentiometer 1
Wiper Terminal for
Potentiometer 1
Ground
No Connect
No Connect
No Connect
No Connect
Bus Serial Clock
Hold
Serial Data Output
Device Address, LSB
No Connect
No Connect
No Connect
No Connect
SCK is the serial clock pin. This pin is used to synchronize
the communication between the microcontroller and the
CAT5411. Opcodes, byte addresses or data present on the SI
pin are latched on the rising edge of the SCK. Data on the SO
pin is updated on the falling edge of the SCK.
A0, A1: Device Address Inputs
These inputs set the device address when addressing
multiple devices. A total of four devices can be addressed on
a single bus. A match in the slave address must be made with
the address input in order to initiate communication with the
CAT5411.
R
H
, R
L
: Resistor End Points
The four sets of R
H
and R
L
pins are equivalent to the
terminal connections on a mechanical potentiometer.
The four R
W
pins are equivalent to the wiper terminal of
a mechanical potentiometer.
CS: Chip Select
R
W
: Wiper
CAT5251 and CS high disables the CAT5411. CS high
takes the SO output pin to high impedance and forces the
devices into a Standby mode (unless an internal write
operation is underway). The CAT5411 draws ZERO current
in the Standby mode. A high to low transition on CS is
required prior to any sequence being initiated. A low to high
transition on CS after a valid write sequence is what initiates
an internal write cycle.
WP: Write Protect
WP is the Write Protect pin. The Write Protect pin will
allow normal read/write operations when held high. When
WP is tied low, all non-volatile write operations to the Data
registers are inhibited (change of wiper control register is
allowed). WP going low while CS is still low will interrupt
a write to the registers. If the internal write cycle has already
been initiated, WP going low will have no effect on any write
operation.
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3
CAT5411
DEVICE OPERATION
The CAT5411 is two resistor arrays integrated with SPI
serial interface logic, two 6-bit wiper control registers and
eight 6-bit, non-volatile memory data registers. Each resistor
array contains 63 separate resistive elements connected in
series. The physical ends of each array are equivalent to the
fixed terminals of a mechanical potentiometer (R
H
and R
L
).
R
H
and R
L
are symmetrical and may be interchanged. The tap
positions between and at the ends of the series resistors are
connected to the output wiper terminals (R
W
) by a CMOS
transistor switch. Only one tap point for each potentiometer
is connected to its wiper terminal at a time and is determined
by the value of the wiper control register. Data can be read or
written to the wiper control registers or the non-volatile
memory data registers via the SPI bus. Additional instructions
allow data to be transferred between the wiper control
registers and each respective potentiometer’s non-volatile
data registers. Also, the device can be instructed to operate in
an “increment/decrement” mode.
SERIAL BUS PROTOCOL
The CAT5041 supports the SPI bus data transmission
protocol. The synchronous Serial Peripheral Interface (SPI)
helps the CAT5411 to interface directly with many of
today’s popular microcontrollers. The CAT5041 contains an
8-bit instruction register. The instruction set and the
operation codes are detailed in the instruction set Table 12.
After the device is selected with CS going low the first
byte will be received. The part is accessed via the SI pin, with
data being clocked in on the rising edge of SCK. The first
byte contains one of the six op-codes that define the
operation to be performed.
Table 2. RELIABILITY CHARACTERISTICS
(Over recommended operating conditions unless otherwise stated.)
Symbol
N
END
(Note 1)
TDR (Note 1)
V
ZAP
(Note 1)
I
LTH
(Note 1)
Parameter
Endurance
Data Retention
ESD Susceptibility
Latch-up
Reference Test Method
MIL−STD−883, Test Method 1033
MIL−STD−883, Test Method 1008
MIL−STD−883, Test Method 3015
JEDEC Standard 17
Min
1,000,000
100
2000
100
Typ
Max
Units
Cycles/Byte
Years
Volts
mA
1. This parameter is tested initially and after a design or process change that affects the parameter.
Table 3. ABSOLUTE MAXIMUM RATINGS
Parameters
Temperature Under Bias
Storage Temperature Range
Voltage to any Pins with Respect to V
SS
(Notes 2, 3)
V
CC
with Respect to GND
Package Power Dissipation Capability (T
A
= 25C)
Lead Soldering Temperature (10 s)
Wiper Current
Ratings
−55
to +125
−65
to +150
−2.0
to V
CC
+2.0
−2.0
to +7.0
1.0
300
12
Units
C
C
V
V
W
C
mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
2. The minimum DC input voltage is –0.5 V. During transitions, inputs may undershoot to –2.0 V for periods of less than 20 ns. Maximum DC
voltage on output pins is V
CC
+0.5 V, which may overshoot to V
CC
+2.0 V for periods of less than 20 ns.
3. Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1 V to V
CC
+1 V.
Table 4. RECOMMENDED OPERATING CONDITIONS
Parameters
V
CC
Industrial Temperature
Ratings
+2.5 to 6.0
−40
to +85
Units
V
C
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CAT5411
Table 5. POTENTIOMETER CHARACTERISTICS
(Over recommended operating conditions unless otherwise stated.)
Symbol
R
POT
R
POT
R
POT
R
POT
Parameter
Potentiometer Resistance (−00)
Potentiometer Resistance (−50)
Potentiometer Resistance (−10)
Potentiometer Resistance (−25)
Potentiometer Resistance Tolerance
R
POT
Matching
Power Rating
I
W
R
W
R
W
V
TERM
V
N
Wiper Current
Wiper Resistance
Wiper Resistance
Voltage on any R
H
or R
L
Pin
Noise
Resolution
Absolute Linearity (Note 5)
Relative Linearity (Note 6)
TC
RPOT
TC
RATIO
C
H
/C
L
/C
W
fc
Temperature Coefficient of R
POT
Ratiometric Temp. Coefficient
Potentiometer Capacitances
Frequency Response
R
W(n)(actual)
−R
(n)(expected)
(Note 8)
R
W(n+1)
−[R
W(n)+LSB
]
(Note 8)
(Note 4)
(Note 4)
(Note 4)
R
POT
= 50 kW (Note 4)
10/10/25
0.4
+300
20
I
W
= +3 mA @ V
CC
= 3 V
I
W
= +3 mA @ V
CC
= 5 V
V
SS
= 0 V
(Note 4)
1.6
+1
+0.2
GND
80
25C, each pot
Test Conditions
Min
Typ
100
50
10
2.5
+20
1
50
+6
300
150
V
CC
Max
Units
kW
kW
kW
kW
%
%
mW
mA
W
W
V
nV/Hz
%
LSB
(Note 7)
LSB
(Note 7)
ppm/C
ppm/C
pF
MHz
4. This parameter is tested initially and after a design or process change that affects the parameter.
5. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a
potentiometer.
6. Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer.
It is a measure of the error in step size.
7. LSB = R
TOT
/ 63 or (R
H
−
R
L
) / 63, single pot
8. n = 0, 1, 2, ..., 63
Table 6. D.C. OPERATING CHARACTERISTICS
(Over recommended operating conditions unless otherwise stated.)
Symbol
I
CC
I
SB
I
LI
I
LO
V
IL
V
IH
V
OL1
Parameter
Power Supply Current
Standby Current (V
CC
= 5 V)
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Output Low Voltage (V
CC
= 3 V)
I
OL
= 3 mA
Test Conditions
f
SCK
= 2 MHz, SO
Open Inputs = GND
V
IN
= GND or V
CC
; SO Open
V
IN
= GND to V
CC
V
OUT
= GND to V
CC
−1
V
CC
x 0.7
Min
Max
1
1
10
10
V
CC
x 0.3
V
CC
+ 1.0
0.4
Units
mA
mA
mA
mA
V
V
V
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