7545 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
REJ03B0140-0106
Rev.1.06
Mar 07, 2008
DESCRIPTION
The 7545 Group is the 8-bit microcomputer based on the 740
family core technology.
The 7545 Group has an 8-bit timer, power-on reset circuit and the
voltage drop detection circuit. Also, Function set ROM is
equipped.
• Clock generating circuit
........................................ Built-in type
(connect to external ceramic resonator or quartz-crystal
oscillator)
• Watchdog timer .........................................................16-bit
×
1
• Power-on reset circuit............................................ Built-in type
• Voltage drop detection circuit................................ Built-in type
• Power source voltage
X
IN
oscillation frequency at ceramic/quartz-crystal oscillation
At 4 MHz .......................................... 1.8 to 3.6 V
• Power dissipation .......................................................... 1.8mW
• Operating temperature range
.................................−20
to 85
°C
APPLICATION
Remote control transmit.
FEATURES
• Basic machine-language instructions .................................. 71
• The minimum instruction execution time .................... 2.00
µs
(at 4 MHz oscillation frequency for the shortest instruction)
• Memory size ROM ........................................ 4K to 60K bytes
RAM ............................................ 256, 512 bytes
• Programmable I/O ports ...................................................... 25
• Key-on wakeup input .................................................. 8 inputs
• LED output port ...................................................................... 8
• Interrupts.................................................... 7 sources, 7 vectors
• Timers .......................................................................... 8-bit
×
3
• Carrier wave generating circuit .......1 channel (8-bit timer
×
2)
PIN CONFIGURATION (TOP VIEW)
P0
4
/KEY
4
P0
3
/KEY
3
P0
5
/KEY
5
P0
6
/KEY
6
P0
7
/KEY
7
P2
0
(LED
0
)/INT
0
P2
1
(LED
1
)/INT
1
P2
2
(LED
2
)
P2
3
(LED
3
)
P2
4
(LED
4
)
P0
2
/KEY
2
P0
1
/KEY
1
P0
0
/KEY
0
P3
7
P3
6
P3
5
16
15
14
24 23 22 21 20 19 18 17
25
26
27
28
29
30
31
32
1
2
3
4
5
6
7
8
M37545Gx-XXXGP
M37545GxGP
13
12
11
10
9
P3
4
P3
3
P3
2
P3
1
P3
0
V
SS
X
OUT
X
IN
Package type: PLQP0032GB-A (32P6U-A)
Fig. 1 Pin configuration (PLQP0032GB-A type)
Rev.1.06 Mar 07, 2008
REJ03B0140-0106
Page 1 of 59
P2
5
(LED
5
)
P2
6
(LED
6
)
P2
7
(LED
7
)
P4
2
/CARR
V
DDR
RESET
CNV
SS
V
CC
7545 Group
PIN CONFIGURATION (TOP VIEW)
P2
1
(LED
1
)/INT
1
P2
2
(LED
2
)
P2
3
(LED
3
)
P2
4
(LED
4
)
P2
5
(LED
5
)
P2
6
(LED
6
)
P2
7
(LED
7
)
P4
2
/CARR
RESET
V
DDR
CNV
SS
V
CC
X
IN
X
OUT
V
SS
P3
0
1
2
3
4
5
32
31
30
29
28
6
7
8
9
10
11
12
13
14
15
16
27
26
25
24
23
22
21
20
19
18
17
P2
0
(LED
0
)/INT
0
P0
7
/KEY
7
P0
6
/KEY
6
P0
5
/KEY
5
P0
4
/KEY
4
P0
3
/KEY
3
P0
2
/KEY
2
P0
1
/KEY
1
P3
7
P0
0
/KEY
0
P3
6
P3
5
P3
4
P3
3
P3
2
P3
1
Package type: PLSP0032JB-A
Fig. 2 Pin configuration (PLSP0032JB-A type)
PIN CONFIGURATION (TOP VIEW)
M37545GxKP
P2
2
(LED
2
)
NC
NC
P2
3
(LED
3
)
P2
4
(LED
4
)
NC
P2
5
(LED
5
)
P2
6
(LED
6
)
P2
7
(LED
7
)
P4
0
(LED
8
)
P4
1
(LED
9
)
P4
2
/CARR
NC
NC
V
DDR
RESET
CNV
SS
V
CC
X
IN
X
OUT
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
P2
1
(LED
1
)/INT
1
P2
0
(LED
0
)/INT
0
P0
7
/KEY
7
P0
6
/KEY
6
P0
5
/KEY
5
P0
4
/KEY
4
P0
3
/KEY
3
P0
2
/KEY
2
P0
1
/KEY
1
P0
0
/KEY
0
P3
7
P3
6
NC
P3
5
P3
4
P3
3
P3
2
P3
1
P3
0
P1
1
P1
0
Package type: 42S1M
Fig. 3 Pin configuration (42S1M type)
M37545RLSS
Rev.1.06 Mar 07, 2008
REJ03B0140-0106
Page 2 of 59
7545 Group
Table 1
Performance overview (1)
Parameter
Function
71
2.00
µs
(Minimum instruction)
M37545G1
M37545G2
M37545G4
M37545G6
M37545G8
M37545GC
M37545GF
RAM
M37545G1/G2
M37545G4/G6/G8/GC/GF
I/O
4096 bytes
×
8 bits
8192 bytes
×
8 bits
16384 bytes
×
8 bits
24576 bytes
×
8 bits
32768 bytes
×
8 bits
49152 bytes
×
8 bits
61440 bytes
×
8 bits
RAM1: 240 bytes
×
8 bits, RAM2: 16 bytes
×
8 bits
RAM1: 384 bytes
×
8 bits, RAM2: 128 bytes
×
8 bits
•
•
•
•
1-bit
×
8
CMOS compatible input level
CMOS 3-state output structure
Whether the pull-up function/key-on wakeup function is to be used or not
can be determined by program.
Number of basic instructions
Instruction execution time
Memory sizes
ROM
I/O port
P0
0
−P0
7
P1
0
, P1
1
I/O (RLSS-only pin)
• 1-bit
×
2
• CMOS compatible input level
• The output structure can be switched to N-channel open-drain or CMOS by software.
•
•
•
•
•
1-bit
×
8
CMOS compatible input level
The output structure can be switched to N-channel open-drain or CMOS by software.
P2 can output a large current for driving LED.
P2
0
and P2
1
are also used as INT
0
and INT
1
, respectively.
P2
0
−P2
7
I/O
P3
0
−P3
7
I/O
• 1-bit
×
8
• CMOS compatible input level
• The output structure can be switched to N-channel open-drain or CMOS by software.
• 1-bit
×
2
• CMOS compatible input level
• CMOS 3-state output structure
•
•
•
•
1-bit
×
1
CMOS compatible input level
CMOS 3-state output structure
Carrier wave output pin for remote-control transmitter
P4
0
, P4
1
I/O (RLSS-only pin)
P4
2
I/O
Timer
Timer 1
Timer 2
Timer 3
8-bit timer with timer 1 latch
Count source is Prescaler output.
8-bit timer with timer 2 primary latch and timer 2 secondary latch
Count source can be selected from f(X
IN
)/16, f(X
IN
)/8, f(X
IN
)/2 or f(X
IN
)/1.
8-bit timer with timer 3 latch
Count source can be selected from f(X
IN
)/16, f(X
IN
)/8 or f(X
IN
)/2 or carrier wave output.
Remote-control waveform is generated by using timer 2 and timer 3.
455 kHz carrier wave generating mode is available.
16-bit
×
1
Built-in
Typ. 1.75 V (Ta=25
°C)
7 sources (External
×
3, Timer
×
3, Software)
Function set ROM is assigned to address FFDA
16
.
Enable/disable of watchdog timer and STP instruction can be selected.
Valid/invaid of voltage drop detection circuit can be selected.
ROM code protect is assigned to address FFDB
16
.
Read/write the built-in QzROM by serial programmer is disabled by setting
“
00
”
to ROM code protect.
CMOS silicon gate
32-pin plastic molded LQFP (PLQP0032GB-A)
32-pin plastic molded SSOP (PLSP0032JB-A)
−20
to 85
°C
1.8 to 3.6 V
Carrier wave generating circuit
Watchdog timer
Power-on reset circuit
Voltage drop detection circuit (Not available for RLSS)
Interrupt
Function set
ROM area
Source
Function set ROM
ROM code protect
Device structure
Package
Operating temperature range
Power source
voltage
f(X
IN
) = 4 MHz
Rev.1.06 Mar 07, 2008
REJ03B0140-0106
Page 3 of 59
7545 Group
Table 2
Performance overview (2)
Parameter
Function
Typ. 0.6 mA (f(X
IN
)=4 MHz, Vcc=3.0 V, output transistors “off” )
Typ. 0.3 mA (f(X
IN
)=4 MHz, Vcc=3.0 V, output transistors “off” , in WIT state,
function except timer 1 disabled)
Typ. 0.1
µA
(Ta = 25
°C,
V
CC
≥
V
DDR
≥
V
CC
−0.6
V, output transistors “off”, in
STP state, all oscillation stopped)
Typ. 0.1
µA
(Ta = 25
°C,
V
DDR
= 1.1 V, 1.8 V
≥
V
CC
≥
0V)
At CPU active
At WIT instruction executed
At STP instruction executed
During reset by voltage drop
detection circuit
Power dissipation
Rev.1.06 Mar 07, 2008
REJ03B0140-0106
Page 4 of 59
FUNCTIONAL BLOCK DIAGRAM (Package: PLQP0032GB-A)
V
SS
V
CC
V
DDR
5
7
6
8
11
7545 Group
Clock input
X
IN
CNV
SS
Clock output
X
OUT
Reset I/O
RESET
P4(1)
P3(8)
P2(8)
P0(8)
4
19 18 17 16 15 14 13 12
3 2 1 32 31 30 29 28
27 26 25 24 23 22 21 20
I/O port P4
I/O port P3
I/O port P2
I/O port P0
Key-on wakeup
Rev.1.06 Mar 07, 2008
REJ03B0140-0106
C P U
9
10
Clock generating circuit
RAM
ROM
A
Prescaler 1 (8)
X
Y
Prescaler 2 (8)
S
PC
H
PC
L
PS
Prescaler 3 (8)
Timer 1(8)
Fig. 4 Functional block diagram (PLQP0032GB-A package)
Page 5 of 59
0
Power-on reset circuit
Reset
Voltage drop
detection circuit
Reset
Carrier wave
generating
circuit
Watchdog timer
Reset
0
INT
1
INT
0
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