WS512K32NV-17H1IA datasheet, PDF

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WS512K32NV-17H1IA: DescriptionSRAM Module, 512KX32, 17ns, CMOS, CPGA66, 1.075 X 1.075 INCH, HERMETIC SEALED, CERAMIC, HIP-66; Categorystorage storage; File Size346KB，7 Pages; ManufacturerWhite Electronic Designs Corporation; Websitehttp://www.wedc.com/

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WS512K32NV-17H1IA Overview

SRAM Module, 512KX32, 17ns, CMOS, CPGA66, 1.075 X 1.075 INCH, HERMETIC SEALED, CERAMIC, HIP-66

WS512K32NV-17H1IA Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
package instruction	1.075 X 1.075 INCH, HERMETIC SEALED, CERAMIC, HIP-66
Reach Compliance Code	unknown
Maximum access time	17 ns
Other features	USER CONFIGURABLE AS 2 X 512K X 16 OR 4 X 512K X 8
I/O type	COMMON
JESD-30 code	S-CPGA-P66
JESD-609 code	e0
length	27.3 mm
memory density	16777216 bit
Memory IC Type	SRAM MODULE
memory width	32
Number of functions	1
Number of terminals	66
word count	524288 words
character code	512000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	512KX32
Output characteristics	3-STATE
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	PGA
Encapsulate equivalent code	PGA66,11X11
Package shape	SQUARE
Package form	GRID ARRAY
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	3.3 V
Certification status	Not Qualified
Maximum seat height	4.6 mm
Maximum standby current	0.06 A
Minimum standby current	3 V
Maximum slew rate	0.6 mA
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	NO
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	TIN LEAD
Terminal form	PIN/PEG
Terminal pitch	2.54 mm
Terminal location	PERPENDICULAR
Maximum time at peak reflow temperature	NOT SPECIFIED
width	27.3 mm
Base Number Matches	1

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White Electronic Designs

512Kx32 SRAM 3.3V MULTICHIP PACKAGE

FEATURES

Access Times of 15, 17, 20ns

Low Voltage Operation

Packaging

• 66-pin, PGA Type, 1.075 inch square, Hermetic

Ceramic HIP (Package 400)

• 68 lead, 22.4mm (0.880 inch) CQFP, (G2U),

3.56mm (0.140"), (Package 510)

Organized as 512Kx32; User Conﬁgurable as

2x512Kx16 or 4x512Kx8

Commercial, Industrial and Military Temperature

Ranges

Low Voltage Operation:

• 3.3V ± 10% Power Supply

Low Power CMOS

WS512K32V-XXX

TTL Compatible Inputs and Outputs

Fully Static Operation:

• No clock or refresh required.

Three State Output.

Built-in Decoupling Caps and Multiple Ground Pins

for Low Noise Operation

Weight

WS512K32V-XG2UX - 8 grams typical

WS512K32NV-XH1X - 13 grams typical

* This product is subject to change without notice.

PIN CONFIGURATION FOR WS512K32NV-XH1X

Top View

I/O

GND

I/O

OE#

I/O

GND

I/O

OE#

0-18

512K x 8

# CS

Pin Description

I/O

0-31

0-18

1-4

OE#

GND

Data Inputs/Outputs

Address Inputs

Write Enables

Chip Selects

Output Enable

Power Supply

Ground

Not Connected

Block Diagram

# CS

I/O

0-7

I/O

8-15

I/O

16-23

I/O

24-31

March 2006

Rev. 12

White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com

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