DS1100M-75+ datasheet, PDF - EEWORLD Datasheet

DS1100M-75+: DescriptionSILICON DELAY LINE, TRUE OUTPUT, PDIP8, 0.300 INCH, DIP-8; Categorylogic logic; File Size836KB，7 Pages; ManufacturerRochester Electronics; Websitehttps://www.rocelec.com/; Environmental Compliance

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DS1100M-75+ Overview

SILICON DELAY LINE, TRUE OUTPUT, PDIP8, 0.300 INCH, DIP-8

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Parts packaging code	DIP
package instruction	DIP,
Contacts	8
Reach Compliance Code	unknown
Is Samacsys	N
JESD-30 code	R-PDIP-T8
JESD-609 code	e3
length	9.375 mm
Logic integrated circuit type	SILICON DELAY LINE
Humidity sensitivity level	NOT SPECIFIED
Number of functions	1
Number of taps/steps	5
Number of terminals	8
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Output impedance nominal value (Z0)	50 Ω
Output polarity	TRUE
Package body material	PLASTIC/EPOXY
encapsulated code	DIP
Package shape	RECTANGULAR
Package form	IN-LINE
Peak Reflow Temperature (Celsius)	260
programmable delay line	NO
Certification status	COMMERCIAL
Maximum seat height	4.572 mm
Maximum supply voltage (Vsup)	5.25 V
Minimum supply voltage (Vsup)	4.75 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	MATTE TIN
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
Total delay nominal (td)	75 ns
width	7.62 mm
Base Number Matches	1

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