MT90222AG2 datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > Wireless rf/communication> Telecom circuit> MT90222AG2

MT90222AG2: DescriptionATM/SONET/SDH Segmentation and Reassembly Device, PBGA384,; CategoryWireless rf/communication Telecom circuit; File Size873KB，155 Pages; ManufacturerMicrosemi; Websitehttps://www.microsemi.com; Environmental Compliance

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MT90222AG2 Overview

ATM/SONET/SDH Segmentation and Reassembly Device, PBGA384,

MT90222AG2 Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Objectid	113286129
Parts packaging code	BGA
Contacts	384
Reach Compliance Code	compliant
JESD-30 code	S-PBGA-B384
Number of terminals	384
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Encapsulate equivalent code	BGA384,26X26,40
Package shape	SQUARE
Package form	GRID ARRAY
Certification status	Not Qualified
Maximum slew rate	425 mA
surface mount	YES
Telecom integrated circuit types	ATM/SONET/SDH SEGMENTATION AND REASSEMBLY DEVICE
Temperature level	INDUSTRIAL
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM

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MT90222/3/4

4/8/16 Port IMA/TC PHY Device

Data Sheet

Features

IMA

•

Up to 16 T1, E1, J1, DSL links & up to 8 IMA

groups with 1 to 16 links/IMA group

Supports symmetrical & asymmetrical operation

CTC (common transmit) & ITC (independent

transmit) clocking modes

Pre-processing of RX ICP (IMA control protocol)

cells

IMA layer & per link statistics and alarms for

performance monitoring with MIB support

•

Ordering Information

MT90222AG

384 Pin PBGA Trays

MT90223AG

384 Pin PBGA Trays

MT90224AG

384 Pin PBGA Trays

MT90222AG2 384 Pin PBGA** Trays, Bake & Drypack

MT90223AG2 384 Pin PBGA** Trays

MT90224AG2 384 Pin PBGA** Trays

**Pb Free Tin/Silver/Copper

-40°C to +85°C

April 2006

HEC (header error control) verification &

generation, error detection, filler cell filtering (IMA

mode) and idle/unassigned cell filtering (TC

mode)

TC layer statistics and error counts i.e. HEC

errors with MIB support

TC and UNI

•

Supports mixed-mode operation: links not

assigned to an IMA group can be used in TC

mode

ATM framing using cell delineation

Standards Compliant

•

ATM Forum - IMA 1.1 (AF-PHY-0086.001) &

backwards compatible with IMA 1.0

ATM Forum - ATM over Fractional T1/E1 (AF-

PHY-0130.00)

ITU G.804 cell mapping & ITU I.432 cell

delineation

•

1. MT90222 supports up to 4 serial links with maximum 4 groups

to be used - groups 0,1,2,3.

MT90223 supports up to 8 serial links

MT90224 supports up to 16 serial links

•

RX External Static RAM

TDM Ring

Utopia

Level 2

BUS

Rx Utopia

FIFo

Internal IMA

Processors

(1 per group)

TDM

Ring

Control

S/P

T1/E1/DSL

Utopia

I/F CTRL

Cell

Delineator

CD Circuits (1 per link)

T1/E1/DSL

P/S

Tx Utopia

FIFo

Transmission

Convergence

TDM

Ring

Control

T1/E1/DSL

Serial TDM Ports

(1 per link, up to 10Mb/s

per link)

TC Circuits (1 per link)

Processor I/F

TDM Ring

Figure 1 - MT90222/3/4 Block Diagram (with Built-in IMA functions for up to 8 IMA Groups over

4/8/16 links)

Zarlink Semiconductor Inc.

Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

MT90222/3/4

General

•

Supports unframed serial streams up to 10 Mb/s per T1/E1 or DSL link

Single chip ATM IMA & TC processor

Versatile TDM interface for most popular T1 or E1 framers and DSL chipsets

Up to 6 MT90222/3/4 devices can be spanned using a TDM ring supporting 32 links

Data Sheet

Provides 8 & 16-bit UTOPIA Level 1 & 2 compatible MPHY Interface (MT90222/3/4 slaved to ATM device)

16-bit microprocessor interface for Intel or Motorola

JTAG test support

2.5 V core, 3.3 V I/O with 5 V tolerant inputs

384 pin PGBA with 1.0 mm pitch balls

MT90222, MT90223 & MT90224 share the same product package and pin-out configuration

Applications

Provides cost effective solutions to implement IMA and/or TC functions over T1, E1, J1 or DSL transport facilities in

broadband access networks. Typical applications are for trunking or subscriber access in:

•

Integrated multi-service access platforms

Access multiplexers

Next-generation DLC

Wireless local loop

3G wireless base-stations

Preamble

The MT90222, MT90223 and MT90224 form a family of similar devices, differing mainly in the maximum number of

serial links, and are collectively referred to as MT90222/3/4. It should be noted throughout this document whenever

reference is made to the number of serial links that the MT90224 offers a maximum of 16 serial links (links 15:0),

while the MT90223 offers a maximum of 8 serial links (links 14,12,10,8,6,4,2 and 0), and the MT90222 offers a

maximum of 4 serial links (links 12, 8, 4 and 0). Pin and register compatibility has been maintained to offer

interchangeability.

Note:

When creating IMA groups for MT90222 the groups 0, 1, 2 and 3 should be used.

Description

The MT90222/3/4 device is targeted to systems implementing the ATM FORUM Inverse Multiplexing for ATM (IMA

version 1.1 and 1.0) or UNI specifications for T1/E1 rates. In the MT90222/3/4 architecture, up to 16 physical and

independent serial links can be terminated through the utilization of off-the-shelf, traditional T1/E1/J1 framers/LIUs

and DSL chip sets. The MT90222/3/4 device can also provide up to 10 Mb/s per link data rates for unframed serial

TDM transmissions for xDSL applications.

The MT90222/3/4 device provides ATM system designers with a flexible architecture when implementing ATM

access over existing trunk interfaces, allowing a migration towards ATM service technology. In addition to the

design of ATM UNI specifications for T1/E1 rates, the MT90222/3/4 device is compliant with the ATM FORUM IMA

specifications for controlling IMA groups of up to 16 trunks in a single chip. The MT90222/3/4 can be configured to

operate in different modes to facilitate the implementation of the IMA function at both CPE and Central Office sites.

For systems targeting ATM over T1/E1 with IMA and TC operating simultaneously, the MT90222/3/4 device

provides the ideal architecture and capabilities.

Zarlink Semiconductor Inc.

MT90222/3/4

Table of Contents

Data Sheet

1.0 Device Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

1.1 Software Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

1.1.1 Link State Machines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

1.1.2 IMA Group State Machines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

1.1.3 Link Addition, Removal or Restoration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

1.1.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

1.1.5 Signalling and Rate Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

1.1.6 Performance Monitoring. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

1.2 Hardware Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

2.0 The ATM Transmit Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

2.1 Cell In Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

2.2 The ATM Transmission Convergence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

2.2.1 TX Cell RAM and TX FIFO Length. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

2.3 Parallel to Serial TDM Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

2.4 ATM Transmit Path in IMA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

2.4.1 IMA Frame Length (M) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

2.4.2 Position of the ICP Cell in the IMA Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

2.4.3 Transmit Clock Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

2.4.4 Stuff Cell Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

2.4.5 IMA Data Cell Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

2.4.6 IMA Controller (RoundRobin Scheduler) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

2.4.7 ICP Cell Generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

2.4.8 IMA Frame Programmable Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

2.4.9 Filler Cell Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

2.4.10 TX IMA Group Start-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

2.4.11 TX Link Addition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

2.4.12 TX Link Deletion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

2.5 ATM Transmit Path in TC Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

3.0 The ATM Receive Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

3.1 Cell Delineation Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

3.1.1 Cell Delineation with Sync signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

3.1.2 Cell Delineation without Sync signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

3.1.3 De-Scrambling and ATM Cell Filtering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

3.2 ATM Receive Path in IMA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

3.2.1 ICP Cell Processor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

3.2.2 IMA Frame Synchronization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

3.2.3 Link Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

3.2.4 RX OAM Label . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

3.2.5 Out of IMA Frame (OIF) Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

3.2.6 Loss of IMA Frame (LIF) Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

3.2.7 Filler Cell Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

3.2.8 Stuff Cell Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

3.2.9 Received ICP Cell Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

3.2.10 Rate Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

3.2.11 Cell Buffer/RAM Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

3.2.12 Cell Sequence Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

3.2.13 Delay Between Links . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

3.2.13.1 RX Recombiner Delay Value. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

3.2.13.2 RX Maximum Operational Delay Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

3.2.13.3 Link Out of Delay Synchronization (LODS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

3.2.13.4 Negative Delay Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

3.2.13.5 Measured Delay Between Links . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Zarlink Semiconductor Inc.

MT90222/3/4

Table of Contents

Data Sheet

3.2.13.6 Incrementing/Decrementing the Recombiner Delay. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

3.2.14 RX IMA Group Start-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

3.2.15 Link Addition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

3.2.16 Link Deletion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

3.2.17 Disabling an IMA Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

3.3 The ATM Receive Path in TC Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

4.0 Description of the TDM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

4.1 Single Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

4.1.1 Single Mode - Generic 1.544 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

4.1.2 Single mode - Generic 2.048 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

4.1.3 Single Mode -ST-BUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

4.2 Wire-OR Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

4.2.1 Wire-OR Mode - 2 Link Grouping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

4.2.2 Wire-OR Mode - 4 Link Grouping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

4.3 Multiplex Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

4.3.1 Multiplex Mode - 2 Link Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

4.3.2 Multiplex Mode - 4 Link Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

4.4 Non-Framed Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

4.4.1 Non-Framed Mode - 2.5 Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

4.4.2 Non-Framed Mode - 5.0 Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

4.4.3 Non-Framed Mode - 10.0 Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

4.5 Clock formats. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

4.6 TDM Loopback Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

4.7 Serial to Parallel (S/P) and Parallel to Serial (P/S) Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

4.8 Clocking Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

4.8.1 Verification of the RXSYNC Period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

4.8.2 Verification of the TXSYNC Period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

4.8.3 Primary and Secondary Reference Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

4.8.4 Verification of Clock Activity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

4.8.5 Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

5.0 UTOPIA Interface Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

5.1 ATM Input Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

5.2 ATM Output Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

5.3 UTOPIA Operation with a Single PHY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

5.4 UTOPIA Operation with Multiple PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

5.5 UTOPIA Operation in TC Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

5.6 UTOPIA Operation in IMA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

5.7 UTOPIA Loopback. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

5.8 Examples of UTOPIA Operations Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

6.0 Support Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

6.1 Counter Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

6.1.1 UTOPIA Input I/F counters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

6.1.2 Transmit TDM I/F Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

6.1.3 Receive TDM I/F Counters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

6.1.4 Access to the Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

6.1.5 Latching counter mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

6.2 Interrupt Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

6.2.1 IRQ Master Status and IRQ Master Enable Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

6.2.2 IRQ Link Status and IRQ Link Enable Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

6.2.2.1 Bit 8 and 7 of IRQ Link 0 Status and IRQ Link 0 Enable Registers. . . . . . . . . . . . . . . . . . . . 70

6.2.3 IRQ Link TC Overflow Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

6.2.4 IRQ IMA Group Overflow Status and Enable Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Zarlink Semiconductor Inc.

MT90222AG2 Related Products

	MT90222AG2	MT90222AG	MT90223AG2	MT90223AG	MT90224AG	MT90224AG2
Description	ATM/SONET/SDH Segmentation and Reassembly Device, PBGA384,	ATM/SONET/SDH Segmentation and Reassembly Device, PBGA384,	ATM NETWORK INTERFACE, PBGA384, 27 X 27 MM, LEAD FREE, PLASTIC, MS-034, BGA-384	ATM NETWORK INTERFACE, PBGA384, 27 X 27 MM, PLASTIC, MS-034, BGA-384	ATM NETWORK INTERFACE, PBGA384, 27 X 27 MM, PLASTIC, MS-034, BGA-384	ATM NETWORK INTERFACE, PBGA384, 27 X 27 MM, LEAD FREE, PLASTIC, MS-034, BGA-384
Is it lead-free?	Lead free	Contains lead	Lead free	Contains lead	Contains lead	Lead free
Parts packaging code	BGA	BGA	BGA	BGA	BGA	BGA
Contacts	384	384	384	384	384	384
Reach Compliance Code	compliant	unknown	compliant	compliant	compliant	compli
JESD-30 code	S-PBGA-B384	S-PBGA-B384	S-PBGA-B384	S-PBGA-B384	S-PBGA-B384	S-PBGA-B384
Number of terminals	384	384	384	384	384	384
Maximum operating temperature	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	BGA	BGA	BGA	BGA	BGA	BGA
Encapsulate equivalent code	BGA384,26X26,40	BGA384,26X26,40	BGA384,26X26,40	BGA384,26X26,40	BGA384,26X26,40	BGA384,26X26,40
Package shape	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE
Package form	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
surface mount	YES	YES	YES	YES	YES	YES
Telecom integrated circuit types	ATM/SONET/SDH SEGMENTATION AND REASSEMBLY DEVICE	ATM/SONET/SDH SEGMENTATION AND REASSEMBLY DEVICE	ATM/SONET/SDH NETWORK INTERFACE	ATM/SONET/SDH NETWORK INTERFACE	ATM/SONET/SDH NETWORK INTERFACE	ATM/SONET/SDH NETWORK INTERFACE
Temperature level	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
Terminal form	BALL	BALL	BALL	BALL	BALL	BALL
Terminal pitch	1 mm	1 mm	1 mm	1 mm	1 mm	1 mm
Terminal location	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM
Is it Rohs certified?	-	incompatible	conform to	incompatible	incompatible	conform to
Maker	-	Microsemi	Microsemi	Microsemi	Microsemi	Microsemi
power supply	-	2.5,3.3,5 V	2.5,3.3,5 V	2.5,3.3,5 V	2.5,3.3,5 V	2.5,3.3,5 V
package instruction	-	-	BGA, BGA384,26X26,40	BGA, BGA384,26X26,40	BGA, BGA384,26X26,40	BGA, BGA384,26X26,40
app	-	-	ATM	ATM	ATM	ATM
JESD-609 code	-	-	e1	e0	e0	e1
length	-	-	27 mm	27 mm	27 mm	27 mm
Humidity sensitivity level	-	-	3	3	3	3
Number of functions	-	-	1	1	1	1
Peak Reflow Temperature (Celsius)	-	-	NOT SPECIFIED	225	225	NOT SPECIFIED
Maximum seat height	-	-	2.28 mm	2.28 mm	2.28 mm	2.28 mm
Nominal supply voltage	-	-	2.5 V	2.5 V	2.5 V	2.5 V
Terminal surface	-	-	Tin/Silver/Copper (Sn/Ag/Cu)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	TIN SILVER COPPER
Maximum time at peak reflow temperature	-	-	NOT SPECIFIED	30	30	NOT SPECIFIED
width	-	-	27 mm	27 mm	27 mm	27 mm

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Shortcut: S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 SA SB SC SD SE SF SG SH SI SJ SK SL SM SN SO SP SQ SR SS ST SU SV SW SX SY SZ T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 TA TB TC TD TE TF TG TH TI TJ TK TL TM TN TO TP TQ TR TS TT TU TV TW TX TY TZ U0 U1 U2 U3 U4 U6 U7 U8 UA UB UC UD UE UF UG UH UI UJ UK UL UM UN UP UQ UR US UT UU UV UW UX UZ V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 VA VB VC VD VE VF VG VH VI VJ VK VL VM VN VO VP VQ VR VS VT VU VV VW VX VY VZ W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 WA WB WC WD WE WF WG WH WI WJ WK WL WM WN WO WP WR WS WT WU WV WW WY X0 X1 X2 X3 X4 X5 X7 X8 X9 XA XB XC XD XE XF XG XH XK XL XM XN XO XP XQ XR XS XT XU XV XW XX XY XZ Y0 Y1 Y2 Y4 Y5 Y6 Y9 YA YB YC YD YE YF YG YH YK YL YM YN YP YQ YR YS YT YX Z0 Z1 Z2 Z3 Z4 Z5 Z6 Z8 ZA ZB ZC ZD ZE ZF ZG ZH ZJ ZL ZM ZN ZP ZR ZS ZT ZU ZV ZW ZX ZY

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