M1AGL600V5-FCSG281 datasheet, PDF

Datasheet> All Categories > Programmable logic devices> Programmable logic> M1AGL600V5-FCSG281

M1AGL600V5-FCSG281: DescriptionField Programmable Gate Array, 13824 CLBs, 600000 Gates, 108MHz, 13824-Cell, CMOS, PBGA281, 10 X 10 MM, 1.05 MM HEIGHT, 0.50 MM PITCH, ROHS COMPLIANT, CSP-281; CategoryProgrammable logic devices Programmable logic; File Size6MB，216 Pages; ManufacturerActel; Websitehttp://www.actel.com/; Environmental Compliance

Download Datasheet Parametric View All

M1AGL600V5-FCSG281 Overview

Field Programmable Gate Array, 13824 CLBs, 600000 Gates, 108MHz, 13824-Cell, CMOS, PBGA281, 10 X 10 MM, 1.05 MM HEIGHT, 0.50 MM PITCH, ROHS COMPLIANT, CSP-281

M1AGL600V5-FCSG281 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Actel
package instruction	10 X 10 MM, 1.05 MM HEIGHT, 0.50 MM PITCH, ROHS COMPLIANT, CSP-281
Reach Compliance Code	compliant
Is Samacsys	N
maximum clock frequency	108 MHz
JESD-30 code	S-PBGA-B281
JESD-609 code	e1
length	10 mm
Humidity sensitivity level	3
Configurable number of logic blocks	13824
Equivalent number of gates	600000
Number of entries	215
Number of logical units	13824
Output times	215
Number of terminals	281
Maximum operating temperature	70 °C
Minimum operating temperature
organize	13824 CLBS, 600000 GATES
Package body material	PLASTIC/EPOXY
encapsulated code	TFBGA
Encapsulate equivalent code	BGA281,19X19,20
Package shape	SQUARE
Package form	GRID ARRAY, THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	260
power supply	1.5 V
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified
Maximum seat height	1.05 mm
Maximum supply voltage	1.575 V
Minimum supply voltage	1.425 V
Nominal supply voltage	1.5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	TIN SILVER COPPER
Terminal form	BALL
Terminal pitch	0.5 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	30
width	10 mm
Base Number Matches	1

Preview

Download Datasheet

View All

v1.4

IGLOO Low-Power Flash FPGAs

with Flash*Freeze Technology

Features and Benefits

Low Power

•

1.2 V to 1.5 V Core Voltage Support for Low Power

Supports Single-Voltage System Operation

5 µW Power Consumption in Flash*Freeze Mode

Low-Power Active FPGA Operation

Flash*Freeze Technology Enables Ultra-Low Power

Consumption while Maintaining FPGA Content

• Easy Entry to / Exit from Ultra-Low-Power Flash*Freeze Mode

High Capacity

• 15 k to 1 Million System Gates

• Up to 144 kbits of True Dual-Port SRAM

• Up to 300 User I/Os

Reprogrammable Flash Technology

•

130-nm, 7-Layer Metal, Flash-Based CMOS Process

Live-at-Power-Up (LAPU) Level 0 Support

Single-Chip Solution

Retains Programmed Design When Powered Off

Clock Conditioning Circuit (CCC) and PLL

• Bank-Selectable I/O Voltages—up to 4 Banks per Chip

• Single-Ended

I/O

Standards:

LVTTL,

LVCMOS

3.3 V / 2.5 V / 1.8 V / 1.5 V / 1.2 V, 3.3 V PCI / 3.3 V PCI-X

†

, and

LVCMOS 2.5 V / 5.0 V Input

†

• Differential I/O Standards: LVPECL, LVDS, B-LVDS, and M-

LVDS (AGL250 and above)

• Wide Range Power Supply Voltage Support per JESD8-B,

Allowing I/Os to Operate from 2.7 V to 3.6 V

• Wide Range Power Supply Voltage Support per JESD8-12,

Allowing I/Os to Operate from 1.14 V to 1.575 V

• I/O Registers on Input, Output, and Enable Paths

• Hot-Swappable and Cold-Sparing I/Os

‡

• Programmable Output Slew Rate

†

and Drive Strength

• Weak Pull-Up/-Down

• IEEE 1149.1 (JTAG) Boundary Scan Test

• Pin-Compatible Packages across the IGLOO Family

†

• Six CCC Blocks, One with an Integrated PLL

• Configurable

Phase

Shift, Multiply/Divide,

Delay

Capabilities, and External Feedback

• Wide Input Frequency Range (1.5 MHz up to 250 MHz)

In-System Programming (ISP) and Security

• Secure ISP Using On-Chip 128-Bit Advanced Encryption

Standard (AES) Decryption (except ARM

-enabled IGLOO

devices) via JTAG (IEEE 1532–compliant)

†

• FlashLock

to Secure FPGA Contents

Embedded Memory

• 1 kbit of FlashROM User Nonvolatile Memory

†

• SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM

Blocks (×1, ×2, ×4, ×9, and ×18 organizations)

†

• True Dual-Port SRAM (except ×18)

High-Performance Routing Hierarchy

• Segmented, Hierarchical Routing and Clock Structure

Advanced I/O

• 700 Mbps DDR, LVDS-Capable I/Os (AGL250 and above)

• 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation

ARM Processor Support in IGLOO FPGAs

• M1 IGLOO Devices—Cortex™-M1 Soft Processor Available

with or without Debug

AGL125

125 k

1,024

3,072

Yes

133

CS196

QN132

VQ100

FG144

AGL250

AGL400

AGL600

AGL1000

M1AGL250 M1AGL400 M1AGL600 M1AGL1000

250 k

400 k

600 k

2,048

–

6,144

9,216

13,824

24,576

108

144

Yes

143

194

235

300

CS196

QN132

4,5

VQ100

FG144

CS196

CS281

IGLOO Product Family

IGLOO Devices

ARM-Enabled IGLOO Devices

System Gates

Typical Equivalent Macrocells

VersaTiles (D-flip-flops)

Flash*Freeze Mode (typical, µW)

RAM kbits (1,024 bits)

4,608-Bit Blocks

FlashROM Bits

Secure (AES) ISP

Integrated PLL in CCCs

VersaNet Globals

I/O Banks

Maximum User I/Os

Package Pins

UC/CS

QFN

VQFP

FBGA

AGL015

15 k

128

384

–

QN68

AGL030

30 k

256

768

–

UC81/CS81

QN48, QN68,

QN132

VQ100

AGL060

60 k

512

1,536

Yes

CS121

QN132

VQ100

FG144

FG144,

FG256,

FG484

FG144,

FG256,

FG484

FG144,

FG256,

FG484

Notes:

1. AES is not available for ARM-enabled IGLOO devices.

AGL060 in CS121 does not support the PLL.

Six chip (main) and twelve quadrant global networks are available for AGL060 and above.

The M1AGL250 device does not support this package.

Device/package support TBD

The

IGLOOe

handbook provides information on higher densities and additional features.

‡ Supported only by AGL015 and AGL030 devices.

† AGL015 and AGL030 devices do not support this feature.

February 2009

1 – IGLOO Device Family Overview

General Description

The IGLOO family of flash FPGAs, based on a 130-nm flash process, offers the lowest power FPGA, a

single-chip solution, small footprint packages, reprogrammability, and an abundance of advanced

features.

The Flash*Freeze technology used in IGLOO devices enables entering and exiting an ultra-low-

power mode that consumes as little as 5 µW while retaining SRAM and register data. Flash*Freeze

technology simplifies power management through I/O and clock management with rapid recovery

to operation mode.

The Low Power Active capability (static idle) allows for ultra-low-power consumption (from 12 µW)

while the IGLOO device is completely functional in the system. This allows the IGLOO device to

control system power management based on external inputs (e.g., scanning for keyboard stimulus)

while consuming minimal power.

Nonvolatile flash technology gives IGLOO devices the advantage of being a secure, low power,

single-chip solution that is live at power-up (LAPU). IGLOO is reprogrammable and offers time-to-

market benefits at an ASIC-level unit cost.

These features enable designers to create high-density systems using existing ASIC or FPGA design

flows and tools.

IGLOO devices offer 1 kbit of on-chip, reprogrammable, nonvolatile FlashROM storage as well as

clock conditioning circuitry based on an integrated phase-locked loop (PLL). The AGL015 and

AGL030 devices have no PLL or RAM support. IGLOO devices have up to 1 million system gates,

supported with up to 144 kbits of true dual-port SRAM and up to 300 user I/Os.

M1 IGLOO devices support the high-performance, 32-bit Cortex-M1 processor developed by ARM

for implementation in FPGAs. Cortex-M1 is a soft processor that is fully implemented in the FPGA

fabric. It has a three-stage pipeline that offers a good balance between low-power consumption

and speed when implemented in an M1 IGLOO device. The processor runs the ARMv6-M instruction

set, has a configurable nested interrupt controller, and can be implemented with or without the

debug block. Cortex-M1 is available for free from Actel for use in M1 IGLOO FPGAs.

The ARM-enabled devices have Actel ordering numbers that begin with M1AGL and do not support

AES decryption.

Flash*Freeze Technology

The IGLOO device offers unique Flash*Freeze technology, allowing the device to enter and exit

ultra-low-power Flash*Freeze mode. IGLOO devices do not need additional components to turn off

I/Os or clocks while retaining the design information, SRAM content, and registers. Flash*Freeze

technology is combined with in-system programmability, which enables users to quickly and easily

upgrade and update their designs in the final stages of manufacturing or in the field. The ability of

IGLOO V2 devices to support a wide range of core voltage (1.2 V to 1.5 V) allows further reduction

in power consumption, thus achieving the lowest total system power.

When the IGLOO device enters Flash*Freeze mode, the device automatically shuts off the clocks

and inputs to the FPGA core; when the device exits Flash*Freeze mode, all activity resumes and

data is retained.

The availability of low-power modes, combined with reprogrammability, a single-chip and single-

voltage solution, and availability of small-footprint, high pin-count packages, make IGLOO devices

the best fit for portable electronics.

v1.4

1-1

Recommended Resources

Inductor thickness measuring circuit

Implementing a high-sensitivity infrared remote control receiving circuit using a dedicated IC

HT-821A0 circuit

Modified circuit diagram of transistor regulated power supply

Micro strain sensor signal conditioning circuit

Pulse edge selection circuit

(3) UART DMA plus IDLE interrupt indefinite length byte reception: The amount of data received by radar applications is relatively large, so DMA is needed to increase the speed and reduce the MCU load. The previous project has used DMA+IDLE interrupt on the STM32F103...; lbbook GD32 MCU

This positioning hole and via are the same as repairing a building.: 3D display adjustment viewThis content is originally created by EEWORLD forum user btty038 . If you want to reprint or use it for commercial purposes, you must obtain the author's consent and indicate...; btty038 PCB Design

SVPWM control of sensored BLDC cannot start when fixed sector 5: STM32F103 chip is used, and the two-way motor driver board is used.It is pure SVPWM control, not FOC. The phase is judged by the sensed HALL.The first motor is driven by TIM1, started, and the speed c...; pingis58 Motor Drive Control（Motor Control）

TMS570 Learning 1- Creating Engineering Lighting: [i=s]This post was last edited by Shi Yu on 2019-8-16 14:57[/i]Software environment: Operating system: Windows 10 IDE：CCS7.4 Code generation tool: HALCoGen 04.07.01 Hardware environment: Target board:...; 石玉 Microcontroller MCU

Arteli AT32 WB415 Bluetooth function development help: [i=s]This post was last edited by General-P on 2022-9-16 08:45[/i]Arteli AT32 WB415 Bluetooth function development help I want to ask if the Bluetooth of Atria AT32 WB415 can directly send the receive...; General-P RF/Wirelessly

[DIY Creative LED] Introduction: [i=s]This post was last edited by dcexpert on 2020-9-12 16:22[/i]The original purpose of this creative LED was to help new colleagues quickly master the hardware development process, including circuit...; dcexpert MCU

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components