CRCA12S1001510271E datasheet, PDF

CRCA12S1001510271E: DescriptionResistor/Capacitor Network, RC NETWORK, TERMINATOR, 0.125W, 51ohm, 50V, 0.00027uF, SURFACE MOUNT, 10, CHIP, LEAD FREE; CategoryPassive components RC network; File Size558KB，2 Pages; ManufacturerVishay; Websitehttp://www.vishay.com; Environmental Compliance

Download Datasheet Parametric View All

CRCA12S1001510271E Overview

Resistor/Capacitor Network, RC NETWORK, TERMINATOR, 0.125W, 51ohm, 50V, 0.00027uF, SURFACE MOUNT, 10, CHIP, LEAD FREE

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Vishay
Reach Compliance Code	unknown
Is Samacsys	N
capacitance	0.00027 µF
Capacitor Negative Tolerance	20%
Capacitor positive tolerance	20%
Capacitor temperature characteristic code	X7R
Capacitor temperature coefficient	15%
The first element resistor	51 Ω
JESD-609 code	e3
length	6.4 mm
Manufacturer's serial number	CRCA
Installation features	SURFACE MOUNT
Network Type	TERMINATOR
Number of capacitor elements	4
Number of functions	1
Number of RC components	4
Number of resistor elements	4
Number of terminals	10
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Package shape	RECTANGULAR PACKAGE
method of packing	TR
Rated (DC) voltage (URdc)	50 V
Rated power dissipation(P)	0.125 W
Rated temperature	70 °C
Resistor tolerance	5%
Resistor temperature coefficient	200 ppm/°C
Resistor/Capacitor Network Type	RC NETWORK
Maximum seat height	0.61 mm
surface mount	YES
technology	METAL GLAZE/THICK FILM
Terminal surface	Matte Tin (Sn)
Terminal pitch	1.27 mm
Terminal shape	WRAPAROUND
width	3.05 mm
Base Number Matches	1

Analog Circuit Practical Knowledge Lectures (12 lectures) in Chinese for free: Browser download: http://cajviewer.cnki.net/cajview_page/CAJViewer5.5.exe Related keywords:Analog circuitlectureChineseknowledge...; fighting Analog electronics

Use FPGA to simulate USB function (written in VHDL language).rar: Use FPGA to simulate USB function (written in VHDL language).rar...; zxopenljx EE_FPGA Learning Park

The internal crystal oscillator of SMIC 5897 is inaccurate: Taking the baud rate of 115200 as an example, the code is written as eight-bit asynchronous. When the serial port debugging assistant communicates, the baud rate is set to 115200 and the stop bit is 1...; 一眼呆 51mcu

KEYENCE Fiber Optic Sensor Disassembly: [i=s]This post was last edited by littleshrimp on 2022-10-23 09:34[/i]What we are going to disassemble this time is a set of Keyence fiber optic sensor combination, which includes a FS-V1 with a scree...; littleshrimp Sensor

FPGA Simplified Design Method Case 4 [12401003385]: [b][font=宋体]Classic cases of minimalist design method[/font]4[/b][align=left] [/align][align=left][font=宋体]Case[/font]4.When receiving en=1, dout generates a high level pulse of 2 clock cycles after 1...; guyu_1 FPGA/CPLD

11 classic software filtering algorithms and their waveform effects (with C language program): Classic software data filtering algorithm (C language program attached on the back page) Note: (the red lines in the image are all filtered) 1. Limiting filtering method (also known as program judgmen...; bqgup Innovation Lab

Shortcut: E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF EG EH EI EJ EK EL EM EN EO EP EQ ER ES ET EU EV EW EX EY EZ F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF FG FH FI FJ FK FL FM FN FO FP FQ FR FS FT FU FV FW FX FY FZ G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 GA GB GC GD GE GF GG GH GI GJ GK GL GM GN GO GP GQ GR GS GT GU GV GW GX GZ H0 H1 H2 H3 H4 H5 H6 H7 H8 HA HB HC HD HE HF HG HH HI HJ HK HL HM HN HO HP HQ HR HS HT HU HV HW HX HY HZ I1 I2 I3 I4 I5 I6 I7 IA IB IC ID IE IF IG IH II IK IL IM IN IO IP IQ IR IS IT IU IV IW IX J0 J1 J2 J6 J7 JA JB JC JD JE JF JG JH JJ JK JL JM JN JP JQ JR JS JT JV JW JX JZ K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 KA KB KC KD KE KF KG KH KI KJ KK KL KM KN KO KP KQ KR KS KT KU KV KW KX KY KZ

Popular Components