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P4C167-35CM

Description
ULTRA HIGH SPEED 16K X 1 STATIC CMOS RAMS
Categorystorage    storage   
File Size192KB,10 Pages
ManufacturerPyramid Semiconductor Corporation
Websitehttp://www.pyramidsemiconductor.com/
Download Datasheet Parametric View All

P4C167-35CM Overview

ULTRA HIGH SPEED 16K X 1 STATIC CMOS RAMS

P4C167-35CM Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerPyramid Semiconductor Corporation
Parts packaging codeDIP
package instructionDIP,
Contacts20
Reach Compliance Codecompli
ECCN code3A001.A.2.C
Maximum access time35 ns
JESD-30 codeR-CDIP-T20
JESD-609 codee0
memory density16384 bi
Memory IC TypeSTANDARD SRAM
memory width1
Number of functions1
Number of terminals20
word count16384 words
character code16000
Operating modeASYNCHRONOUS
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
organize16KX1
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codeDIP
Package shapeRECTANGULAR
Package formIN-LINE
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)NOT SPECIFIED
Certification statusNot Qualified
Maximum seat height5.08 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyCMOS
Temperature levelMILITARY
Terminal surfaceTIN LEAD
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width7.62 mm
Base Number Matches1
P4C167/P4C167L
ULTRA HIGH SPEED 16K X 1
STATIC CMOS RAMS
FEATURES
Full CMOS, 6T Cell
High Speed (Equal Access and Cycle Times)
– 10/12/15/20/25 ns (Commercial)
– 12/15/20/25/35 ns (Industrial)
– 15/20/25/35/45 ns (Military)
Low Power Operation
Single 5V±10% Power Supply
Data Retention with 2.0V Supply (P4C167L
Military)
Separate Data I/O
Three-State Output
TTL Compatible Output
Fully TTL Compatible Inputs
Standard Pinout (JEDEC Approved)
– 20-Pin 300 mil DIP
– 20-Pin 300 mil SOJ
– 20-Pin LCC
DESCRIPTION
The P4C167/L are 16,384-bit high speed static RAMs or-
ganized as 16K x 1. The CMOS memories require no clocks
or refreshing and have equal access and cycle times. The
RAMs operate from a single 5V ± 10% tolerance power
supply. Data integrity is maintained for supply voltages
down to 2.0V, typically drawing 10µA.
Access times as fast as 10 nanoseconds are available,
greatly enhancing system speeds. CMOS reduces power
consumption to low levels.
The P4C167/L are available in 20-pin 300 mil DIP, 20-pin
300 mil SOJ, and 20-pin LCC packages providing excel-
lent board level densities.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATIONS
DIP (P2, C6)
SOJ (J2) SIMILAR
LCC (L9)
Document #
SRAM106
REV A
1
Revised October 2005
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