AV9172-07CN16 datasheet, PDF - EEWORLD Datasheet

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AV9172-07CN16: DescriptionPLL Based Clock Driver, 6 True Output(s), 0 Inverted Output(s), CMOS, PDIP16, 0.300 INCH, PLASTIC, DIP-16; Categorylogic logic; File Size397KB，8 Pages; ManufacturerIDT (Integrated Device Technology)

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AV9172-07CN16 Overview

PLL Based Clock Driver, 6 True Output(s), 0 Inverted Output(s), CMOS, PDIP16, 0.300 INCH, PLASTIC, DIP-16

AV9172-07CN16 Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	IDT (Integrated Device Technology)
Parts packaging code	DIP
package instruction	0.300 INCH, PLASTIC, DIP-16
Contacts	16
Reach Compliance Code	not_compliant
Is Samacsys	N
Input adjustment	STANDARD
JESD-30 code	R-PDIP-T16
JESD-609 code	e0
length	19.05 mm
Logic integrated circuit type	PLL BASED CLOCK DRIVER
Number of functions	1
Number of inverted outputs
Number of terminals	16
Actual output times	6
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	DIP
Package shape	RECTANGULAR
Package form	IN-LINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Certification status	Not Qualified
Same Edge Skew-Max（tskwd）	0.25 ns
Maximum supply voltage (Vsup)	5.25 V
Minimum supply voltage (Vsup)	4.75 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	TIN LEAD
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	7.62 mm
minfmax	100 MHz
Base Number Matches	1

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Integrated

Circuit

Systems, Inc.

AV9172

Low Skew Output Buffer

General Description

The

AV9172

is designed to generate low skew clocks for

clock distribution in high-performance PCs and workstations.

It uses phase-locked loop technology to align the phase and

frequency of the output clocks with an input reference clock.

Because the input to output skew is guaranteed to ±500ps, the

part acts as a “zero delay” buffer.

The

AV9172

has six configurable outputs. The

AV9172-01

version has one output that runs at the same phase and

frequency as the reference clock. A second output runs at the

same frequency as the reference, but can either be in phase or

180° out of phase from the input clock. Two outputs are

provided that are at twice the reference frequency and in

phase with the reference clock. The final outputs can be

programmed to be replicas of the 2x clocks or non-overlapping

two phase clocks at twice the reference frequency. The

AV9172-01

and

AV9172-03

operates with input clocks

from 10 MHz to 50 MHz while producing outputs from

10 MHz to 100 MHz. The

AV9172-07

operates with input

clocks from 20 to 100 MHz.

The use of a phase-locked loop (PLL) allows the output

clocks to run at multiples of the input clock. This permits

routing of a lower speed clock and local generation of a

required high speed clock. Synchronization of the phase

relationship between the input clock and the output clocks is

accomplished when one output clock is connected to the

input pin FBIN. The PLL circuitry matches rising edges of the

input clock and output clocks.

Features

AV9172-07

input is 66 MHz with 66 and 33 MHz

output buffers

• AV9172-01

is pin compatible with Gazelle GA1210E

• ±250ps skew (max) between outputs

• ±500ps skew (max) between input and outputs

• Input frequency range from 10 MHz to 50 MHz

(-01, -03) and from 20 MHz to 100 MHz (-07)

• Output frequency range from 10 MHz to 100 MHz

(-01, -03, -07)

• Special mode for two-phase clock generation

• Inputs and outputs are fully TTL-compatible

• CMOS process results in low power supply current

• High drive, 25mA outputs

• Low cost

• 16-pin SOIC (150-mil) or 16-pin PDIP package

The

AV9172

is fabricated using CMOS technology which

results in much lower power consumption and cost compared

with the gallium arsenide-based GA1210E. The typical

operating current for the

AV9172

is 50mA versus 120mA for

the GA1210E.

ICS offers several versions of the

AV9172.

The different

devices are shown below:

PART

AV9172-01

AV9172-03

AV9172-07

DESCRIPTION

Second source of GA1210E

Clock doubler and buffer

Clock buffer for 66 MHz input

•

Block Diagram

AV9172RevB060297P

ICS reserves the right to make changes in the device data identified in this publication

without further notice. ICS advises its customers to obtain the latest version of all

device data to verify that any information being relied upon by the customer is current

and accurate.

AV9172-07CN16 Related Products

	AV9172-07CN16	AV9172-07CC16	AV9172-07CW16	AV9172-07CS16
Description	PLL Based Clock Driver, 6 True Output(s), 0 Inverted Output(s), CMOS, PDIP16, 0.300 INCH, PLASTIC, DIP-16	PLL Based Clock Driver, 6 True Output(s), 0 Inverted Output(s), CMOS, CDIP16, CERDIP-16	PLL Based Clock Driver, 6 True Output(s), 0 Inverted Output(s), CMOS, PDSO16, 0.300 INCH, PLASTIC, SOIC-16	PLL Based Clock Driver, 6 True Output(s), 0 Inverted Output(s), CMOS, PDSO16, 0.150 INCH, SOIC-16
Is it lead-free?	Contains lead	Contains lead	Contains lead	Contains lead
Is it Rohs certified?	incompatible	incompatible	incompatible	incompatible
Maker	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)
Parts packaging code	DIP	DIP	SOIC	SOIC
package instruction	0.300 INCH, PLASTIC, DIP-16	CERDIP-16	0.300 INCH, PLASTIC, SOIC-16	0.150 INCH, SOIC-16
Contacts	16	16	16	16
Reach Compliance Code	not_compliant	not_compliant	not_compliant	not_compliant
Is Samacsys	N	N	N	N
Input adjustment	STANDARD	STANDARD	STANDARD	STANDARD
JESD-30 code	R-PDIP-T16	R-GDIP-T16	R-PDSO-G16	R-PDSO-G16
JESD-609 code	e0	e0	e0	e0
Logic integrated circuit type	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER
Number of functions	1	1	1	1
Number of terminals	16	16	16	16
Actual output times	6	6	6	6
Maximum operating temperature	70 °C	70 °C	70 °C	70 °C
Package body material	PLASTIC/EPOXY	CERAMIC, GLASS-SEALED	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	DIP	DIP	SOP	SOP
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	IN-LINE	IN-LINE	SMALL OUTLINE	SMALL OUTLINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Same Edge Skew-Max（tskwd）	0.25 ns	0.25 ns	0.25 ns	0.25 ns
Maximum supply voltage (Vsup)	5.25 V	5.25 V	5.25 V	5.25 V
Minimum supply voltage (Vsup)	4.75 V	4.75 V	4.75 V	4.75 V
Nominal supply voltage (Vsup)	5 V	5 V	5 V	5 V
surface mount	NO	NO	YES	YES
technology	CMOS	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal surface	TIN LEAD	TIN LEAD	TIN LEAD	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE	THROUGH-HOLE	GULL WING	GULL WING
Terminal location	DUAL	DUAL	DUAL	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
minfmax	100 MHz	100 MHz	100 MHz	100 MHz
Base Number Matches	1	1	1	1
length	19.05 mm	-	10.3 mm	9.9 mm
Terminal pitch	2.54 mm	-	1.27 mm	1.27 mm
width	7.62 mm	-	7.3406 mm	3.9 mm

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