NXP Semiconductors
Technical Data
Document Number: MC33879
Rev. 11.0, 7/2016
Configurable octal serial switch with
open load detect current disable
The 33879 device is an 8-output hardware configurable, high-side/low-side
switch with 16-bit serial input control using the serial peripheral interface (SPI).
Two of the outputs may be controlled directly via a microcontroller for pulse-
width modulation (PWM) applications. The 33879 incorporates SMARTMOS
technology, with CMOS logic, bipolar/MOS analog circuitry, and DMOS power
MOSFETs. The 33879 controls various inductive, incandescent, or LED loads by
directly interfacing with a microcontroller. The circuit’s innovative monitoring and
protection features include very low standby currents, cascade fault reporting,
internal + 45 V clamp voltage for low-side configuration, - 20 V high-side
configuration, output specific diagnostics, and independent overtemperature
protection.
Features
•
•
•
•
•
•
•
•
•
•
•
Designed to operate 5.5 V < V
PWR
< 27.5 V
16-bit SPI for control and fault reporting, 3.3 V / 5.0 V compatible
Outputs are current limited (0.6 to 1.2 A) to drive incandescent lamps
Output voltage clamp, + 45 V (low-side) and - 20 V (high-side) during
inductive switching
On/Off control of open load detect current (LED application)
Internal reverse battery protection on V
PWR
Loss of ground or supply will not energize loads or damage IC
Maximum 5.0
μA
I
PWR
standby current at 13 V V
PWR
R
DS(ON)
of 0.75
Ω
at 25
°C
typical
Short-circuit detect and current limit with automatic retry
Independent overtemperature protection
33879
33879A
HIGH-SIDE/ LOW-SIDE SWITCH
EK SUFFIX (PB-FREE)
98ARL10543D
32-PIN SOICW
Applications
•
•
•
•
•
•
Solenoids
Relays
Actuators
Stepper motors
Brush DC motors
Incandescent lamps
V
PWR
5.0 V
V
BAT
33879
VPWR
VDD
D1
D2
D3
D4
S1
S2
S3
S4
M
D5
D6
D7
D8
S5
S6
S7
S8
High-side Drive
MCU
A0
MOSI
SCLK
CS
MISO
PWM1
PWM2
EN
DI
SCLK
CS
D0
IN5
IN6
GND
H-Bridge Configuration
V
BAT
V
BAT
Low-side Drive
Figure 1. 33879 simplified application diagram
© 2016 NXP B.V.
1
Orderable parts
Table 1. Orderable part variations
Part number
(1)
MC33879APEK
MC33879TEK
Temperature (T
A
)
-40 to 125
°
C
Package
32 SOICW-EP
Notes
1. To order parts in Tape & Reel, add the R2 suffix to the part number.
Table 2. Device variations
Symbol
V
PWR
V
PWR
Supply Voltage
• 33879
• 33879A
Output Fault Detection Current @ Threshold, High-side Configuration
I
OUT(FLT-TH)
Outputs Programmed OFF
• 33879
• 33879A
Output OFF Open Load Detection Current, High-side Configuration
VDRAIN = 16 V, VSOURCE = 0 V, Outputs Programmed OFF,
I
OCO
VPWR = 16 V
• 33879
• 33879A
Output OFF Open Load Detection Current, Low-side Configuration
VDRAIN = 16 V, VSOURCE = 0 V, Outputs Programmed OFF,
I
OCO
VPWR =16 V
• 333879
• 338979A
EN Pull-down Current
I
EN
EN = 5.0 V
• 333879
• 33879A
Output Fault Detection Voltage Threshold
V
OUT(FLT-TH)
Outputs Programmed OFF
• 33879
• 33879A
Output Fault Detection Current @ Threshold, Low-side Configuration
I
OUT(FLT-TH)
Outputs Programmed OFF
• 33879
• 33879A
20
20
30
30
60
115
μA
2.5
2.5
4.0
4.0
4.5
5.0
V
20
20
45
45
100
110
μA
μA
40
40
75
75
135
150
μA
65
60
100
100
160
190
35
35
55
55
90
150
μA
Characteristic
Min.
-16
-16
Typ.
–
–
Max.
40
45
Unit
V
33879
2
NXP Semiconductors
2
Internal block diagram
VDD
VPWR
~50
μA
Internal
Bias
Power Supply
Charge
Pump
Overvoltage
Shutdown/POR
Sleep State
GND
OV, POR, SLEEP
Typical of all 8 output drivers
TLIM
SPI Bit 0
~50
μA
Enable
SPI Bit 4
Gate
Drive
Control
Current
Limit
+
‚
__
CS
SCLK
DI
DO
EN
~110 kΩ
SPI and
Interface
Logic
D1
D2
Open
Load
Detect
Current
~80
μA
D3
IN5
D4
D7
Drain
Outputs
D8
S1
S2
S3
S4
S7
S8
D5
IN6
~50
μA
IN5
+
‚
+
‚
Open/Short
Comparator
~4.0 V Open/Short
Threshold
Source
Outputs
TLIM
Gate
Drive
Control
Current
Limit
+
‚
EP
Exposed Pad
Open
Load
Detect
Current
~80
μA
D6
Drain
Outputs
S5
+
+
‚
‚
S6
Source
Outputs
Open/Short
Comparator
~4.0 V Open/Short
Threshold
Figure 2. 33879 simplified internal block diagram
33879
NXP Semiconductors
3
3
3.1
Pin connections
Pinout diagram
GND
VDD
S8
NC
D8
S2
D2
NC
NC
S1
D1
D6
S6
IN6
EN
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
GND
DO
VPWR
NC
S7
D7
S4
D4
NC
NC
S3
D3
D5
S5
IN5
CS
DI
Figure 3. 33879 pin connections
3.2
Pin definitions
A functional description of each pin can be found in
5.1, Functional pin description, page 15.
Table 3. 33879 pin definitions
Pin number
1
2
3
4, 8, 9, 24,
25, 30
5
6
7
10
11
12
13
14
15
16
17
18
19
20
Pin name
GND
V
DD
S8
Pin function
Ground
Input
Output
No
Connection
Output
Output
Output
Output
Output
Output
Output
Input
Input
Clock
Input
Input
Input
Output
Formal name
Ground
Digital ground.
Definition
Logic Supply Voltage Logic supply for SPI interface. With V
DD
low the device is in Sleep mode.
Source Output 8
Not Connected
Drain Output 8
Source Output 2
Drain Output 2
Source Output 1
Drain Output 1
Drain Output 6
Source Output 6
Command Input 6
Enable Input
SPI Clock
Serial Data Input
SPI Chip Select
Command Input 5
Source Output 5
Output 8 MOSFET source pin.
No internal connection to this pin.
Output 8 MOSFET drain pin.
Output 2 MOSFET source pin.
Output 2 MOSFET drain pin.
Output 1 MOSFET source pin.
Output 1 MOSFET drain pin.
Output 6 MOSFET drain pin.
Output 6 MOSFET source pin.
PWM direct control input pin for output 6. IN6 is “OR” with SPI bit.
IC Enable. Active high. With EN low, the device is in Sleep mode.
SPI control clock input pin.
SPI control data input pin from MCU to the 33879. Logic [1] activates output.
SPI control chip select input pin from MCU to the 33879. Logic [0] allows data to be
transferred in.
PWM direct control input pin for output 5. IN5 is “OR” with SPI bit.
Output 5 MOSFET source pin.
NC
D8
S2
D2
S1
D1
D6
S6
IN6
EN
SCLK
DI
CS
IN5
S5
33879
4
NXP Semiconductors
Table 3. 33879 pin definitions (continued)
Pin number
21
22
23
26
27
28
29
31
32
33
Pin name
D5
D3
S3
D4
S4
D7
S7
V
PWR
DO
EP
Pin function
Output
Output
Output
Output
Output
Output
Output
Input
Output
Ground
Formal name
Drain Output 5
Drain Output 3
Source Output 3
Drain Output 4
Source Output 4
Drain Output 7
Source Output 7
Battery Input
Serial Data Output
Exposed Pad
Output 5 MOSFET drain pin.
Output 3 MOSFET drain pin.
Output 3 MOSFET source pin.
Output 4 MOSFET drain pin.
Output 4 MOSFET source pin.
Output 7 MOSFET drain pin.
Output 7 MOSFET source pin.
Power supply pin to the 33879. V
PWR
has internal reverse battery protection.
SPI control data output pin from the 33879 to the MCU. DO = 0 no fault, DO = 1 specific
output has fault.
Device performs as specified with the Exposed Pad un-terminated (floating) however,
it is recommended the exposed pad be terminated to pin 1 (GND) and system ground.
Definition
33879
NXP Semiconductors
5
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