16 Mbit Dual-Bank Flash + 2/4 Mbit SRAM ComboMemory
SST34HF162G / SST34HF164G
SST34HF162G/164G16Mb Dual-Bank Flash + 2/4 Mb SRAM MCP ComboMemory
Preliminary Specifications
FEATURES:
• Flash Organization: 1M x16
– 16 Mbit: 12 Mbit + 4 Mbit
• Concurrent Operation
– Read from or Write to SRAM while
Erase/Program Flash
• SRAM Organization:
– 2 Mbit:128K x16
– 4 Mbit: 256K x16
• Single 2.7-3.3V Read and Write Operations
• Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
• Low Power Consumption: (typical values @ 5 MHz)
– Active Current: Flash 10 mA (typical)
SRAM 6 mA (typical)
– Standby Current: 10 µA (typical)
• Hardware Sector Protection (WP#)
– Protects 4 outer most sectors (4 KWord) in the
larger bank by holding WP# low and unprotects
by holding WP# high
• Hardware Reset Pin (RST#)
– Resets the internal state machine to reading
data array
• Sector-Erase Capability
– Uniform 2 KWord sectors
• Block-Erase Capability
– Uniform 32 KWord blocks
• Read Access Time
– Flash: 70 ns
– SRAM: 70 ns
• Erase-Suspend / Erase-Resume Capabilities
• Latched Address and Data
• Fast Erase and Word-Program (typical):
– Sector-Erase Time: 18 ms
– Block-Erase Time: 18 ms
– Chip-Erase Time: 35 ms
– Program Time: 7 µs
• Automatic Write Timing
– Internal
V
PP
Generation
• End-of-Write Detection
– Toggle Bit
– Data# Polling
• CMOS I/O Compatibility
• JEDEC Standard Command Set
• Packages Available
– 48-ball LFBGA (6mm x 8mm)
– 48-ball LBGA (10mm x 12mm)
– Non-Pb (lead-free) packages available
PRODUCT DESCRIPTION
The SST34HF16xG ComboMemory devices integrate a
1M x16 CMOS flash memory bank with either 128K x16 or
256K x16 CMOS SRAM memory bank in a multi-chip
package (MCP). These devices are fabricated using SST’s
proprietary, high-performance CMOS SuperFlash technol-
ogy incorporating the split-gate cell design and thick-oxide
tunneling injector to attain better reliability and manufactur-
ability compared with alternate approaches. The
SST34HF16xG devices are ideal for applications such as
cellular phones, GPS devices, PDAs, and other portable
electronic devices in a low power and small form factor sys-
tem.
The SuperFlash technology provides fixed Erase and Pro-
gram times, independent of the number of Erase/Program
cycles that have occurred. Therefore, the system software
or hardware does not have to be modified or de-rated as is
necessary with alternative flash technologies, whose Erase
and Program times increase with accumulated Erase/Pro-
gram cycles. The SST34HF16xG devices offer a guaran-
teed endurance of 10,000 cycles. Data retention is rated at
greater than 100 years. With high-performance Program
©2004 Silicon Storage Technology, Inc.
S71276-00-000
11/04
1
operations, the flash memory banks provide a typical Pro-
gram time of 7 µsec. The entire flash memory bank can be
erased and programmed word-by-word in 4 seconds (typi-
cally) for the SST34HF16xG, when using interface features
such as Toggle Bit or Data# Polling to indicate the comple-
tion of Program operation. To protect against inadvertent
flash write, the SST34HF16xG devices contain on-chip
hardware and software data protection schemes.
The flash and SRAM operate as two independent memory
banks with respective bank enable signals. The memory
bank selection is done by two bank enable signals. The
SRAM bank enable signal, BES#, selects the SRAM bank.
The flash memory bank enable signal, BEF#, has to be
used with Software Data Protection (SDP) command
sequence when controlling the Erase and Program opera-
tions in the flash memory bank. The memory banks are
superimposed in the same memory address space where
they share common address lines, data lines, WE# and
OE# which minimize power consumption and area. See
Figure 1 for memory organization.
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
ComboMemory is a trademark of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
16 Mbit Dual-Bank Flash + 2/4 Mbit SRAM ComboMemory
SST34HF162G / SST34HF164G
Preliminary Specifications
Designed, manufactured, and tested for applications requir-
ing low power and small form factor, the SST34HF16xG
are offered in both commercial and extended temperatures
and a small footprint package to meet board space con-
straint requirements. See Figure 2 for pin assignments.
Flash Program Operation
These devices are programmed on a word-by-word basis.
Before programming, one must ensure that the sector
which is being programmed is fully erased.
The Program operation is accomplished in three steps:
Device Operation
The SST34HF16xG use BES# and BEF# to control opera-
tion of either the flash or the SRAM memory bank. When
BEF# is low, the flash bank is activated for Read, Program
or Erase operation. When BES# is low the SRAM is acti-
vated for Read and Write operation. BEF# and BES# can-
not be at low level at the same time.
If all bank enable
signals are asserted, bus contention will result and the
device may suffer permanent damage.
All address,
data, and control lines are shared by flash and SRAM
memory banks which minimizes power consumption and
loading. The device goes into standby when BEF# and
BES# bank enables are raised to V
IHC
(Logic High) or
when BEF# is high.
1. Software Data Protection is initiated using the
three-byte load sequence.
2. Address and data are loaded.
During the Program operation, the addresses are
latched on the falling edge of either BEF# or WE#,
whichever occurs last. The data is latched on the
rising edge of either BEF# or WE#, whichever
occurs first.
3. The internal Program operation is initiated after
the rising edge of the fourth WE# or BEF#, which-
ever occurs first. The Program operation, once ini-
tiated, will be completed typically within 7 µs.
See Figures 8 and 9 for WE# and BEF# controlled Pro-
gram operation timing diagrams and Figure 21 for flow-
charts. During the Program operation, the only valid reads
are Data# Polling and Toggle Bit. During the internal Pro-
gram operation, the host is free to perform additional tasks.
Any commands issued during an internal Program opera-
tion are ignored.
Concurrent Read/Write Operation
The SST34HF16xG provide the unique benefit of being
able to read from or write to SRAM, while simultaneously
erasing or programming the flash. This allows data alter-
ation code to be executed from SRAM, while altering the
data in flash. The following table lists all valid states.
C
ONCURRENT
R
EAD
/W
RITE
S
TATE
T
ABLE
Flash
Program/Erase
Program/Erase
SRAM
Read
Write
Flash Sector- /Block-Erase Operation
These devices offer both Sector-Erase and Block-Erase
operations. These operations allow the system to erase the
devices on a sector-by-sector (or block-by-block) basis.
The sector architecture is based on a uniform sector size of
2 KWord. The Block-Erase mode is based on a uniform
block size of 32 KWord. The Sector-Erase operation is initi-
ated by executing a six-byte command sequence with a
Sector-Erase command (30H) and sector address (SA) in
the last bus cycle. The Block-Erase operation is initiated by
executing a six-byte command sequence with Block-Erase
command (50H) and block address (BA) in the last bus
cycle. The sector or block address is latched on the falling
edge of the sixth WE# pulse, while the command (30H or
50H) is latched on the rising edge of the sixth WE# pulse.
The internal Erase operation begins after the sixth WE#
pulse. Any commands issued during the Block- or Sector-
Erase operation are ignored except Erase-Suspend and
Erase-Resume. See Figures 13 and 14 for timing wave-
forms.
The device will ignore all SDP commands when an Erase
or Program operation is in progress. Note that Product
Identification commands use SDP; therefore, these com-
mands will also be ignored while an Erase or Program
operation is in progress.
Flash Read Operation
The Read operation of the SST34HF16xG is controlled by
BEF# and OE#, both have to be low for the system to
obtain data from the outputs. BEF# is used for device
selection. When BEF# is high, the chip is deselected and
only standby power is consumed. OE# is the output control
and is used to gate data from the output pins. The data bus
is in high impedance state when either BEF# or OE# is
high. Refer to the Read cycle timing diagram for further
details (Figure 7).
©2004 Silicon Storage Technology, Inc.
S71276-00-000
11/04
2
16 Mbit Dual-Bank Flash + 2/4 Mbit SRAM ComboMemory
SST34HF162G / SST34HF164G
Preliminary Specifications
Flash Chip-Erase Operation
The SST34HF16xG provide a Chip-Erase operation, which
allows the user to erase all sectors/blocks to the “1” state.
This is useful when the device must be quickly erased.
The Chip-Erase operation is initiated by executing a six-
byte command sequence with Chip-Erase command (10H)
at address 555H in the last byte sequence. The Erase
operation begins with the rising edge of the sixth WE# or
BEF#, whichever occurs first. During the Erase operation,
the only valid read is Toggle Bits or Data# Polling. See
Table 5 for the command sequence, Figure 12 for timing
diagram, and Figure 24 for the flowchart. Any commands
issued during the Chip-Erase operation are ignored.
The actual completion of the nonvolatile write is asynchro-
nous with the system; therefore, either a Data# Polling
(DQ
7
) or Toggle Bit (DQ
6
) read may be simultaneous with
the completion of the Write cycle. If this occurs, the system
may possibly get an erroneous result, i.e., valid data may
appear to conflict with either DQ
7
or DQ
6
. In order to pre-
vent spurious rejection, if an erroneous result occurs, the
software routine should include a loop to read the
accessed location an additional two (2) times. If both reads
are valid, then the device has completed the Write cycle,
otherwise the rejection is valid.
Flash Data# Polling (DQ
7
)
When the device is in an internal Program operation, any
attempt to read DQ
7
will produce the complement of the
true data. Once the Program operation is completed, DQ
7
will produce true data. During internal Erase operation, any
attempt to read DQ
7
will produce a ‘0’. Once the internal
Erase operation is completed, DQ
7
will produce a ‘1’. The
Data# Polling is valid after the rising edge of fourth WE# (or
BEF#) pulse for Program operation. For Sector-, Block-, or
Chip-Erase, the Data# Polling is valid after the rising edge
of sixth WE# (or BEF#) pulse. See Figure 10 for Data# Poll-
ing (DQ
7
) timing diagram and Figure 22 for a flowchart.
Toggle Bits (DQ
6
and DQ
2
)
During the internal Program or Erase operation, any con-
secutive attempts to read DQ
6
will produce alternating “1”s
and “0”s, i.e., toggling between 1 and 0. When the internal
Program or Erase operation is completed, the DQ
6
bit will
stop toggling. The device is then ready for the next opera-
tion. The toggle bit is valid after the rising edge of the fourth
WE# (or BEF#) pulse for Program operations. For Sector-,
Block-, or Chip-Erase, the toggle bit (DQ
6
) is valid after the
rising edge of sixth WE# (or BEF#) pulse. DQ
6
will be set to
“1” if a Read operation is attempted on an Erase-sus-
pended Sector/Block. If Program operation is initiated in a
sector/block not selected in Erase-Suspend mode, DQ
6
will
toggle.
An additional Toggle Bit is available on DQ
2
, which can be
used in conjunction with DQ
6
to check whether a particular
sector is being actively erased or erase-suspended. Table 1
shows detailed status bit information. The Toggle Bit (DQ
2
)
is valid after the rising edge of the last WE# (or BEF#)
pulse of a Write operation. See Figure 11 for Toggle Bit tim-
ing diagram and Figure 22 for a flowchart.
Flash Erase-Suspend/-Resume Operations
The Erase-Suspend operation temporarily suspends a
Sector- or Block-Erase operation thus allowing data to be
read from any memory location, or program data into any
sector/block that is not suspended for an Erase operation.
The operation is executed by issuing a one-byte command
sequence with Erase-Suspend command (B0H). The
device automatically enters read mode within 20 µs after
the Erase-Suspend command had been issued. Valid data
can be read from any sector or block that is not suspended
from an Erase operation. Reading at address location
within erase-suspended sectors/blocks will output DQ
2
tog-
gling and DQ
6
at “1”. While in Erase-Suspend mode, a Pro-
gram operation is allowed except for the sector or block
selected for Erase-Suspend. To resume Sector-Erase or
Block-Erase operation which has been suspended, the
system must issue an Erase-Resume command. The
operation is executed by issuing a one-byte command
sequence with Erase Resume command (30H) at any
address in the one-byte sequence.
Flash Write Operation Status Detection
The SST34HF16xG provides two software means to
detect the completion of a Write (Program or Erase)
cycle, in order to optimize the system Write cycle time.
The software detection includes two status bits: Data#
Polling (DQ
7
) and Toggle Bit (DQ
6
). The End-of-Write
detection mode is enabled after the rising edge of WE#,
which initiates the internal Program or Erase operation.
©2004 Silicon Storage Technology, Inc.
S71276-00-000
11/04
3
16 Mbit Dual-Bank Flash + 2/4 Mbit SRAM ComboMemory
SST34HF162G / SST34HF164G
Preliminary Specifications
TABLE 1: W
RITE
O
PERATION
S
TATUS
Status
Normal
Operation
Standard
Program
Standard
Erase
Erase-
Suspend
Mode
Read From
Erase
Suspended
Sector/
Block
Read From
Non-Erase
Suspended
Sector/
Block
Program
DQ
7
DQ7#
0
1
DQ
6
Toggle
Toggle
1
DQ
2
No Toggle
Toggle
Toggle
Hardware Reset (RST#) - L3K only
The RST# pin provides a hardware method of resetting the
device to read array data. When the RST# pin is held low
for at least T
RP,
any in-progress operation will terminate and
return to Read mode (see Figure 18). When no internal
Program/Erase operation is in progress, a minimum period
of T
RHR
is required after RST# is driven high before a valid
Read can take place (see Figure 17).
The Erase operation that has been interrupted needs to be
reinitiated after the device resumes normal operation mode
to ensure data integrity. See Figures 17 and 18 for timing
diagrams.
Software Data Protection (SDP)
The SST34HF16xG provide the JEDEC standard Software
Data Protection scheme for all data alteration operations,
i.e., Program and Erase. Any Program operation requires
the inclusion of the three-byte sequence. The three-byte
load sequence is used to initiate the Program operation,
providing optimal protection from inadvertent Write opera-
tions, e.g., during the system power-up or power-down.
Any Erase operation requires the inclusion of six-byte
sequence. The SST34HF16xG are shipped with the Soft-
ware Data Protection permanently enabled. See Table 5 for
the specific software command codes. During SDP com-
mand sequence, invalid commands will abort the device to
Read mode within T
RC.
The contents of DQ
15
-DQ
8
are
“Don’t Care” during any SDP command sequence.
Data
Data
Data
DQ7#
Toggle
No Toggle
T1.0 1276
Note:
DQ
7,
DQ
6,
and DQ
2
require a valid address when reading
status information.
Data Protection
The SST34HF16xG provide both hardware and software
features to protect nonvolatile data from inadvertent writes.
Hardware Data Protection
Noise/Glitch Protection: A WE# or BEF# pulse of less than
5 ns will not initiate a Write cycle.
V
DD
Power Up/Down Detection: The Write operation is
inhibited when V
DD
is less than 1.5V.
Write Inhibit Mode: Forcing OE# low, BEF# high, or WE#
high will inhibit the Write operation. This prevents inadvert-
ent writes during power-up or power-down.
Hardware Block Protection
The SST34HF16xG provide a hardware block protection
which protects the outermost 8 KWord in Bank 1. The block
is protected when WP# is held low. See Figure 1 for Block-
Protection location.
A user can disable block protection by driving WP# high
thus allowing erase or program of data into the protected
sectors. WP# must be held high prior to issuing the write
command and remain stable until after the entire Write
operation has completed.
©2004 Silicon Storage Technology, Inc.
S71276-00-000
11/04
4
16 Mbit Dual-Bank Flash + 2/4 Mbit SRAM ComboMemory
SST34HF162G / SST34HF164G
Preliminary Specifications
Product Identification
The Product Identification mode identifies the device as
SST34HF162G or SST34HF164G and the manufacturer
as SST. This mode may be accessed by software opera-
tions only. The hardware device ID Read operation, which
is typically used by programmers cannot be used on this
device because of the shared lines between flash and
SRAM in the multi-chip package. Therefore, application of
high voltage to pin A
9
may damage this device. Users may
use the software Product Identification operation to identify
the part (i.e., using the device ID) when using multiple man-
ufacturers in the same socket. For details, see Tables 4 and
5 for software operation, Figure 15 for the Software ID
Entry and Read timing diagram and Figure 23 for the ID
Entry command sequence flowchart.
TABLE 2: P
RODUCT
I
DENTIFICATION
ADDRESS
Manufacturer’s ID
Device ID
SST34HF16xG
BK0001H
734BH
T2.0 1276
SRAM Operation
With BES# low and BEF# high, the SST34HF162G/164G
operate as either 128K x16 or 256K x16 CMOS SRAM,
with fully static operation requiring no external clocks or
timing strobes. The SST34HF162G/164G SRAM is
mapped into the first 128 KWord address space. When
BES# and BEF# are high, all memory banks are dese-
lected and the device enters standby. Read and Write
cycle times are equal. The control signals UBS# and LBS#
provide access to the upper data byte and lower data byte.
See Table 4 for SRAM Read and Write data byte control
modes of operation.
SRAM Read
The SRAM Read operation of the SST34HF162G/164G is
controlled by OE# and BES#, both have to be low with
WE# high for the system to obtain data from the outputs.
BES# is used for SRAM bank selection. OE# is the output
control and is used to gate data from the output pins. The
data bus is in high impedance state when OE# is high.
Refer to the Read cycle timing diagram, Figure 4, for fur-
ther details.
SRAM Write
The SRAM Write operation of the SST34HF162G/164G is
controlled by WE# and BES#, both have to be low for the
system to write to the SRAM. During the Word-Write oper-
ation, the addresses and data are referenced to the rising
edge of either BES# or WE# whichever occurs first. The
write time is measured from the last falling edge of BES#
or WE# to the first rising edge of BES# or WE#. Refer to
the Write cycle timing diagrams, Figures 5 and 6, for fur-
ther details.
DATA
00BFH
BK0000H
Note:
BK = Bank Address (A
19
-A
18
)
Product Identification Mode Exit
In order to return to the standard Read mode, the Software
Product Identification mode must be exited. Exit is accom-
plished by issuing the Software ID Exit command
sequence, which returns the device to the Read mode.
This command may also be used to reset the device to the
Read mode after any inadvertent transient condition that
apparently causes the device to behave abnormally, e.g.,
not read correctly. Please note that the Software ID Exit
command is ignored during an internal Program or Erase
operation. See Table 5 for software command codes, Fig-
ure 16 for timing waveform and Figure 23 for a flowchart.
©2004 Silicon Storage Technology, Inc.
S71276-00-000
11/04
5
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