White Electronic Designs
128Kx16 SRAM/EEPROM MODULE
FEATURES
Access Times of 35ns (SRAM) and 150ns (EEPROM)
Access Times of 45ns (SRAM) and 120ns (EEPROM)
Access Times of 70ns (SRAM) and 300ns (EEPROM)
Packaging
• 66 pin, PGA Type, 1.075" square HIP, Hermetic
Ceramic HIP (H1) (Package 400)
• 68 lead, Hermetic CQFP (G2T), 22mm (0.880")
square (Package 509). Designed to fit JEDEC 68
lead 0.990" CQFJ footprint (FIGURE 2)
128Kx16 SRAM
128Kx16 EEPROM
Organized as 128Kx16 of SRAM and 128Kx16 of
EEPROM Memory with separate Data Buses
Both blocks of memory are User Configurable as
256Kx8
Low Power CMOS
WSE128K16-XXX
PRELIMINARY*
Commercial, Industrial and Military Temperature
Ranges
TTL Compatible Inputs and Outputs
Built-in Decoupling Caps and Multiple Ground Pins
for Low Noise Operation
Weight - 13 grams typical
EEPROM MEMORY FEATURES
Write Endurance 10,000 Cycles
Data Retention at 25°C, 10 Years
Low Power CMOS Operation
Automatic Page Write Operation
Page Write Cycle Time 10ms Max.
Data Polling for End of Write Detection
Hardware and Software Data Protection
TTL Compatible Inputs and Outputs
* This product is under development, is not qualified or characterized and is subject to
change without notice.
FIGURE 1 – WSE128K16-XH1X PIN
CONFIGURATION
Top View
1
SD
8
SD
9
SD
10
A
13
A
14
A
15
A
16
NC
SD
0
SD
1
SD
2
11
22
12
SWE
2
#
SCS
2
#
GND
SD
11
A
10
A
11
A
12
V
CC
SCS
1
#
NC
SD
3
33
23
SD
15
SD
14
SD
13
SD
12
OE#
NC
SWE#
1
SD
7
SD
6
SD
5
SD
4
ED
8
ED
9
ED
10
A
6
A
7
NC
A
8
A
9
ED
0
ED
1
ED
2
44
34
V
CC
ECS
2
#
EWE
2
#
ED
11
A
3
A
4
A
5
EWE
1
#
ECS
1
#
GND
ED
3
55
45
ED
15
ED
14
ED
13
ED
12
A
0
A
1
A
2
ED
7
ED
6
ED
5
ED
5
66
56
PIN DESCRIPTION
ED
0-15
SD
0-15
A
0-16
SWE#
1-2
SCS#
1-2
OE#
V
CC
GND
NC
EWE#
1-2
ECS#
1-2
EEPROM Data Inputs/Outputs
SRAM Data Inputs/Outputs
Address Inputs
SRAM Write Enable
SRAM Chip Selects
Output Enable
Power Supply
Ground
Not Connected
EEPROM Write Enable
EEPROM Chip Select
BLOCK DIAGRAM
SWE
1
# SCS
1
#
OE#
A
0-16
128K x 8
SRAM
128K x 8
SRAM
128K x 8
EEPROM
128K x 8
EEPROM
SWE
2
# SCS
2
#
EWE
1
# ECS
1
#
EWE
2
# ECS
2
#
8
8
8
8
SD
0 - 7
SD
8 - 1 5
ED
0 - 7
ED
8 - 1 5
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2005
Rev. 3
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
FIGURE 2 WSE128K16-XG2TX PIN CONFIGURATION
Top View
NC
A
0
A
1
A
2
A
3
A
4
A
5
ECS
1
#
GND
ECS
2
#
SWE
1
#
A
6
A
7
A
8
A
9
A
10
V
CC
WSE128K16-XXX
PRELIMINARY
PIN DESCRIPTION
ED
0-15
SD
0-15
A
0-16
SWE#
1-2
SCS#
1-2
OE#
V
CC
GND
NC
EWE#
1-2
ECS#
1-2
EEPROM Data Inputs/Outputs
SRAM Data Inputs/Outputs
Address Inputs
SRAM Write Enable
SRAM Chip Selects
Output Enable
Power Supply
Ground
Not Connected
EEPROM Write Enable
EEPROM Chip Select
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
SD
0
SD
1
SD
2
SD
3
SD
4
SD
5
SD
6
SD
7
GND
SD
8
SD
9
SD
10
SD
11
SD
12
SD
13
SD
14
SD
15
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
A
16
SCS
1
#
OE#
SCS
2
#
NC
SWE
2
#
EWE
1
#
EWE
2
#
NC
NC
NC
A
12
A
13
A
14
V
CC
A
15
A
11
ED
0
ED
1
ED
2
ED
3
ED
4
ED
5
ED
6
ED
7
GND
ED
8
ED
9
ED
10
ED
11
ED
12
ED
13
ED
14
ED
15
OE#
A
0-16
BLOCK DIAGRAM
SWE
1
# SCS
1
#
SWE
2
# SCS
2
#
EWE
1
# ECS
1
#
EWE
2
# ECS
2
#
128K x 8
SRAM
128K x 8
SRAM
128K x 8
EEPROM
128K x 8
EEPROM
8
8
8
8
SD
0 - 7
SD
8 - 1 5
ED
0 - 7
ED
8 - 1 5
0.940"
The WEDC 68 lead G2T CQFP fills the same fit and
function as the JEDEC 68 lead CQFJ or 68 PLCC. But
the G2T has the TCE and lead inspection advantage
of the CQFP form.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2005
Rev. 3
2
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
ABSOLUTE MAXIMUM RATINGS
Parameter
Operating Temperature
Storage Temperature
Signal Voltage Relative to GND
Junction Temperature
Supply Voltage
Symbol
T
A
T
STG
V
G
T
J
V
CC
Min
-55
-65
-0.5
-0.5
Max
+125
+150
V
CC
+0.5
150
7.0
Unit
°C
°C
V
°C
V
Parameter
Supply Voltage
Input High Voltage
Input Low Voltage
Operating Temp. (Mil.)
WSE128K16-XXX
PRELIMINARY
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
IH
V
IL
T
A
Min
4.5
2.0
-0.3
-55
Max
5.5
V
CC
+ 0.3
+0.8
+125
Unit
V
V
V
°C
EEPROM TRUTH TABLE
CAPACITANCE
T
A
= +25°C
Parameter
OE# capacitance
WE#
1-4
capacitance
HIP (PGA)
CQFP G2T
CS#
1-4
capacitance
Data I/O capacitance
Address input capacitance
Symbol Conditions
C
OE
V
IN
= 0 V, f = 1.0 MHz
C
WE
C
CS
C
I/O
C
AD
V
IN
= 0 V, f = 1.0 MHz
V
IN
= 0 V, f = 1.0 MHz
V
I/O
= 0 V, f = 1.0 MHz
V
IN
= 0 V, f = 1.0 MHz
Max Unit
50 pF
20
20
20
20
50
pF
pF
pF
pF
CS#
H
L
L
X
X
X
OE#
X
L
H
H
X
L
WE#
X
H
L
X
H
X
Mode
Standby
Read
Write
Out Disable
Write
Inhibit
Data I/O
High Z
Data Out
Data In
High Z/Data Out
SRAM TRUTH TABLE
SCS# OE# SWE#
H
X
X
L
L
H
L
H
H
Mode
Standby
Read
Read
Data I/O
High Z
Data Out
High Z
Power
Standby
Active
Active
This parameter is guaranteed by design but not tested.
L
X
L
Write
Data In
Active
DC CHARACTERISTICS
V
CC
= 5.0V, GND = 0V, -55°C ≤ T
A
≤ +125°C
Parameter
Input Leakage Current
Output Leakage Current
SRAM Operating Supply Current x 16 Mode
Standby Current
(35 to 45ns)
SRAM Output Low Voltage
(70ns)
(35 to 45ns)
SRAM Output High Voltage
(70ns)
EEPROM Operating Supply Current x 16 Mode
EEPROM Output Low Voltage
EEPROM Output High Voltage
Symbol
I
LI
I
LO
I
CC
x16
ISB
V
OL
V
OL
V
OH
V
OH
I
CC1
V
OL
V
OH1
Conditions
V
CC
= 5.5, V
IN
= GND to V
CC
SCS# = V
IH
, OE# = V
IH
, V
OUT
= GND to V
CC
SCS# = V
IL
, OE# = ECS# = V
IH
, f = 5MHz, V
CC
= 5.5
ECS# = SCS# = V
IH
, OE# = V
IH
, f = 5MHz, V
CC
= 5.5
I
OL
= 8.0mA, V
CC
= 4.5
I
OL
= 2.1mA, V
CC
= 4.5
I
OH
= -4.0mA, V
CC
= 4.5
I
OH
= -1mA, V
CC
= 4.5
ECS# = V
IL
, OE# = SCS# = V
IH
I
OL
= 2.1 mA, V
CC
= 4.5V
I
OH
= 400 µA, V
CC
= 4.5V
Min
Max
10
10
360
31.2
0.4
0.4
Unit
µA
µA
mA
mA
V
V
V
V
mA
V
V
2.4
2.4
155
0.45
2.4
NOTES:
1. The I
CC
current listed includes both the DC operating current and the frequency dependent component (@ 5 MHz).
The frequency component typically is less than 2 mA/MHz, with OE at V
IH
.
2. DC test conditions: V
IL
= 0.3V, V
IH
= V
CC
- 0.3V
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2005
Rev. 3
3
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
SRAM AC CHARACTERISTICS
V
CC
= 5.0V, GND = 0V, -55°C ≤ T
A
≤ +125°C
Parameter
Read Cycle
Read Cycle Time
Address Access Time
Output Hold from Address Change
Chip Select Access Time
Output Enable to Output Valid
Chip Select to Output in Low Z
Output Enable to Output in Low Z
Chip Disable to Output in High Z
Output Disable to Output in High Z
1. This parameter is guaranteed by design but not tested.
WSE128K16-XXX
PRELIMINARY
Symbol
t
RC
t
AA
t
OH
t
ACS
t
OE
t
CLZ1
t
OLZ1
t
CHZ1
t
OHZ1
-35
Min
35
35
0
35
20
3
0
20
20
3
0
0
Max
Min
45
-45
Max
45
5
45
25
5
5
20
20
Min
70
-70
Max
70
70
35
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
25
25
SRAM AC CHARACTERISTICS
V
CC
= 5.0V, GND = 0V, -55°C ≤ T
A
≤ +125°C
Parameter
Write Cycle
Write Cycle Time
Chip Select to End of Write
Address Valid to End of Write
Data Valid to End of Write
Write Pulse Width
Address Setup Time
Address Hold Time
Output Active from End of Write
Write Enable to Output in High Z
Data Hold Time
1. This parameter is guaranteed by design but not tested.
Symbol
t
WC
t
CW
t
AW
t
DW
t
WP
t
AS
t
AH
t
OW1
t
WHZ1
t
DH
-35
Min
35
25
25
20
25
0
0
4
0
Max
Min
45
30
30
25
30
0
0
4
0
-45
Max
Min
70
60
60
30
50
5
5
5
0
-70
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
25
25
FIGURE 3 – AC TEST CIRCUIT
I
OL
Current Source
AC TEST CONDITIONS
Parameter
Input Pulse Levels
Input Rise and Fall
Input and Output Reference Level
Output Timing Reference Level
Typ
V
IL
= 0, V
IH
= 3.0
5
1.5
1.5
Unit
V
ns
V
V
D.U.T.
C
eff
= 50 pf
V
Z
≈ 1.5V
(Bipolar Supply)
I
OH
Current Source
NOTES:
V
Z
is programmable from -2V to +7V.
I
OL
& I
OH
programmable from 0 to 16mA.
Tester Impedance Z0 = 75 Ω.
V
Z
is typically the midpoint of V
OH
and V
OL
.
I
OL
& I
OH
are adjusted to simulate a typical resistive load circuit.
ATE tester includes jig capacitance.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2005
Rev. 3
4
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
FIGURE 4 – SRAM READ CYCLES
WSE128K16-XXX
PRELIMINARY
t
RC
ADDRESS
t
RC
ADDRESS
t
AA
t
OH
SRAM
DATA I/O
PREVIOUS DATA VALID
DATA VALID
SOE#
SRAM
DATA I/O
SCS#
t
AA
t
ACS
t
CLZ
t
OE
t
OLZ
HIGH IMPEDANCE
t
CHZ
t
OHZ
DATA VALID
READ CYCLE 1, (SCS# = OE# = V
IL
, SWE# = V
IH
)
READ CYCEL 2, (SWE# = V
IH
)
FIGURE 5 – SRAM WRITE CYCLE SWE# CONTROLLED
t
WC
ADDRESS
t
AW
t
CW
SCS#
t
AH
t
AS
SWE#
t
WP
t
OW
t
WHZ
t
DW
t
DH
DATA VALID
SRAM
DATA I/O
WRITE CYCLE 1, SWE# CONTROLLED
FIGURE 6 – SRAM WRITE CYCEL SCS# CONTROLLED
t
WC
ADDRESS
t
AS
SCS#
t
WP
SWE#
t
DW
SRAM
DATA I/O
t
DH
t
AW
t
CW
t
AH
DATA VALID
WRITE CYCLE 2, SCS# CONTROLLED
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2005
Rev. 3
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
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