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X25057V-1.8

Description
5MHz Low Power SPI Serial E 2 PROM with IDLock⑩ Memory
File Size338KB,16 Pages
ManufacturerICmic
Websitehttp://www.icmic.com/
Download Datasheet View All

X25057V-1.8 Overview

5MHz Low Power SPI Serial E 2 PROM with IDLock⑩ Memory

This X25057 device has been acquired by
IC MICROSYSTEMS from Xicor, Inc.
ICmic
TM
IC MICROSYSTEMS
4K
X25057
5MHz Low Power SPI Serial E
2
PROM with IDLock™ Memory
DESCRIPTION
512 x 8 Bit
FEATURES
•5MHz Clock Rate
•IDLock™ Memory
—IDLock First or Last Page, Any 1/4 or Lower 1/2 of
2
E PROM Array
The X25057 is a CMOS 4K-bit serial E PROM, internally
organized as 512 x 8. The X25057 features a Serial
2
Peripheral Interface (SPI) and software protocol allowing
operation on a simple four-wire bus. The bus
signals are a clock input (SCK) plus separate data in (SI)
and data out (SO) lines. Access to the device is
controlled through a chip select (CS) input, allowing any
number of devices to share the same bus.
IDLock is a programmable locking mechanism which
allows the user to lock system ID and parametric data in
•Low Power CMOS
—<1∝A Standby Current
—<3mA Active Current during Write —
<400∝A Active Current during Read
•1.8V to 3.6V, 2.7V-5.5V or 4.5V to 5.5V Operation
•Built-in Inadvertent Write Protection
—Power-Up/Power-Down Protection Circuitry —
Write Enable Latch
—Write Protect Pin
•SPI Modes (0,0 & 1,1)
•512 x 8 Bits
different portions of the E
2
PROM memory space, ranging
from as little as one page to as much as 1/2 of
the total array. The X25057 also features a WP pin that can
be used for hardwire protection of the part, disabling
—16 Byte Page Mode
•Self-Timed Write Cycle
—5ms Write Cycle Time (Typical)
•High Reliability
—Endurance: 100,000 Cycles/Byte
—Data Retention: 100 Years
—ESD: 2000V on all pins
•8-Lead MSOP Package •8-
Lead TSSOP Package
•8-Lead SOIC Package
•8-Lead PDIP Package
FUNCTIONAL DIAGRAM
SI
SO
COMMAND
DECODE
AND
CONTROL
all write attempts, as well as a Write Enable Latch that
must be set before a write operation can be initiated.
The X25057 utilizes Xicor’s proprietary Direct Write
providing a minimum endurance of 100,000 cycles
TM
cell,
per byte and a minimum data retention of 100 years.
DATA REGISTER
Y DECODE LOGIC
16
8
SCK
X
DECODE
LOGIC
32
LOGIC
4K E PROM
ARRAY
2
(512 x 8)
CS
WP
WRITE CONTROL LOGIC
HIGH VOLTAGE
CONTROL
7033 FRM F01
Characteristics subject to change without notice
©Xicor,
Inc. 1994 – 1997 Patents
Pending 7033-1.1 5/8/97 T1/C0/D0 SH
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