IDT70V27S55G datasheet, PDF - EEWORLD Datasheet

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IDT70V27S55G: Description32K X 16 DUAL-PORT SRAM, 35 ns, PQFP100; Categorystorage; File Size209KB，21 Pages; ManufacturerIDT (Integrated Device Technology, Inc.); Websitehttp://www.idt.com/

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IDT70V27S55G Overview

32K X 16 DUAL-PORT SRAM, 35 ns, PQFP100

IDT70V27S55G Parametric

Parameter Name	Attribute value
Number of functions	1
Number of terminals	100
Maximum operating temperature	85 Cel
Minimum operating temperature	-40 Cel
Maximum supply/operating voltage	3.6 V
Minimum supply/operating voltage	3 V
Rated supply voltage	3.3 V
maximum access time	35 ns
Processing package description	14 X 14 MM, 1.40 MM HEIGHT, TQFP-100
state	ACTIVE
Craftsmanship	CMOS
packaging shape	SQUARE
Package Size	FLATPACK, LOW PROFILE, FINE PITCH
surface mount	Yes
Terminal form	GULL WING
Terminal spacing	0.5000 mm
terminal coating	TIN LEAD
Terminal location	QUAD
Packaging Materials	PLASTIC/EPOXY
Temperature level	INDUSTRIAL
memory width	16
organize	32K X 16
storage density	524288 deg
operating mode	ASYNCHRONOUS
Number of digits	32768 words
Number of digits	32K
Memory IC type	DUAL-PORT SRAM
serial parallel	PARALLEL

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HIGH-SPEED 3.3V

32K x 16 DUAL-PORT

STATIC RAM

IDT70V27S/L

LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018

Features:

◆

True Dual-Ported memory cells which allow simultaneous

access of the same memory location

High-speed access

– Commercial: 15/20/25/35/55ns (max.)

– Industrial: 15/20/35ns (max.)

Low-power operation

– IDT70V27S

Active: 500mW (typ.)

Standby: 3.3mW (typ.)

– IDT70V27L

Active: 500mW (typ.)

Standby: 660

W (typ.)

Separate upper-byte and lower-byte control for bus

matching capability

On-chip port arbitration logic

◆

Dual chip enables allow for depth expansion without

external logic

IDT70V27 easily expands data bus width to 32 bits or more

using the Master/Slave select when cascading more than

one device

M/S = V

for

BUSY

output flag on Master,

M/S = V

for

BUSY

input on Slave

Busy and Interrupt Flags

Full on-chip hardware support of semaphore signaling

between ports

Fully asynchronous operation from either port

LVTTL-compatible, single 3.3V (±0.3V) power supply

Available in 100-pin Thin Quad Flatpack (TQFP)

Industrial temperature range (-40°C to +85°C) is available

for selected speeds

Green parts available, see ordering information

Functional Block Diagram

R/W

I/O

8-15L

I/O

0-7L

BUSY

(1,2)

I/O

Control

I/O

Control

I/O

8-15R

I/O

0-7R

BUSY

(1,2)

14L

Address

Decoder

14L

32Kx16

MEMORY

ARRAY

70V27

Address

Decoder

14R

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

14R

SEM

INT

(2)

SEM

(2)

INT

3603 drw 01

NOTES:

BUSY

is an input as a Slave (M/S=V

) and an output as a Master (M/S=V

BUSY

and

INT

are non-tri-state totem-pole outputs (push-pull).

JULY 2018

DSC 3603/16

6.01

2018

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