XCR3032-10PC44C datasheet, PDF

Datasheet> All Categories > Programmable logic devices> Programmable logic> XCR3032-10PC44C

XCR3032-10PC44C: Description32 Macrocell CPLD; CategoryProgrammable logic devices Programmable logic; File Size198KB，14 Pages; ManufacturerXILINX; Websitehttps://www.xilinx.com/

Download Datasheet Parametric View All

XCR3032-10PC44C Overview

32 Macrocell CPLD

XCR3032-10PC44C Parametric

Parameter Name	Attribute value
Maker	XILINX
Parts packaging code	LCC
package instruction	QCCJ,
Contacts	44
Reach Compliance Code	unknow
maximum clock frequency	57 MHz
JESD-30 code	S-PQCC-J44
length	16.5862 mm
Dedicated input times	2
Number of I/O lines	33
Number of terminals	44
Maximum operating temperature	70 °C
Minimum operating temperature
organize	2 DEDICATED INPUTS, 33 I/O
Output function	MACROCELL
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Package shape	SQUARE
Package form	CHIP CARRIER
Programmable logic type	EE PLD
propagation delay	13 ns
Certification status	Not Qualified
Maximum seat height	4.57 mm
Maximum supply voltage	3.6 V
Minimum supply voltage	3 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
width	16.5862 mm

Preview

Download Datasheet

View All

xcr3032.fm Page 1 Monday, October 9, 2000 6:44 PM

This product has been discontinued. Please see

www.xilinx.com/partinfo/notify/pdn0007.htm

for details.

APPLICATION NOTE

XCR3032: 32 Macrocell CPLD

14*

DS038 (v1.3) October 9, 2000

Product Specification

CMOS process technology

and

the patented full CMOS

FZP design technique. For 5V applications, Xilinx also

offers the high speed XCR5032 CPLD that offers pin-to-pin

speeds of 6 ns.

The Xilinx FZP CPLDs utilize the patented XPLA

(eXtended Programmable Logic Array) architecture. The

XPLA architecture combines the best features of both PLA

and PAL type structures to deliver high speed and flexible

logic allocation that results in superior ability to make

design changes with fixed pinouts. The XPLA structure in

each logic block provides a fast 8 ns PAL path with five ded-

icated product terms per output. This PAL path is joined by

an additional PLA structure that deploys a pool of 32 prod-

uct terms to a fully programmable OR array that can allo-

cate the PLA product terms to any output in the logic block.

This combination allows logic to be allocated efficiently

throughout the logic block and supports as many as 37

product terms on an output. The speed with which logic is

allocated from the PLA array to an output is only 2.5 ns,

regardless of the number of PLA product terms used, which

results in worst case t

's of only 10.5 ns from any pin to

any other pin. In addition, logic that is common to multiple

outputs can be placed on a single PLA product term and

shared across multiple outputs via the OR array, effectively

increasing design density.

The XCR3032 CPLDs are supported by industry standard

CAE tools (Cadence/OrCAD, Exemplar Logic, Mentor,

Synopsys, Synario, Viewlogic, and Synplicity), using text

(ABEL, VHDL, Verilog) and/or schematic entry. Design ver-

ification uses industry standard simulators for functional

and timing simulation. Development is supported on per-

sonal computer, Sparc, and HP platforms. Device fitting

uses a Xilinx developed tool, XPLA Professional (available

on the Xilinx web site).

The XCR3032 CPLD is reprogrammable using industry

standard device programmers from vendors such as Data

I/O, BP Microsystems, SMS, and others.

Features

•

Industry's first TotalCMOS™ PLD - both CMOS design

and process technologies

Fast Zero Power (FZP™) design technique provides

ultra-low power and very high speed

High speed pin-to-pin delays of 8ns

Ultra-low static power of less than 35

100% routable with 100% utilization while all pins and

all macrocells are fixed

Deterministic timing model that is extremely simple to

use

Two clocks available

Programmable clock polarity at every macrocell

Support for asynchronous clocking

Innovative XPLA™ architecture combines high speed

with extreme flexibility

1000 erase/program cycles guaranteed

20 years data retention guaranteed

Logic expandable to 37 product terms

PCI compliant

Advanced 0.5

CMOS process

Security bit prevents unauthorized access

Design entry and verification using industry standard

and Xilinx CAE tools

Reprogrammable using industry standard device

programmers

Innovative Control Term structure provides either sum

terms or product terms in each logic block for:

- Programmable 3-state buffer

- Asynchronous macrocell register preset/reset

Programmable global 3-state pin facilitates ‘bed of nails'

testing without using logic resources

Available in both PLCC and VQFP packages

•

Description

The XCR3032 CPLD (Complex Programmable Logic

Device) is the first in a family of CoolRunner

CPLDs from

Xilinx. These devices combine high speed and zero power

in a 32 macrocell CPLD. With the FZP design technique,

the XCR3032 offers true pin-to-pin speeds of 8 ns, while

simultaneously delivering power that is less than 35

A at

standby without the need for “turbo bits” or other power

down schemes. By replacing conventional sense amplifier

methods for implementing product terms (a technique that

has been used in PLDs since the bipolar era) with a cas-

caded chain of pure CMOS gates, the dynamic power is

also substantially lower than any competing CPLD. These

devices are the first TotalCMOS PLDs, as they use both a

DS038 (v1.3) October 9, 2000

www.xilinx.com

1-800-255-7778

Recommended Resources

One of the battery charge status indication circuits

DC servo constant current power amplifier 02

RTS766/RTS767 circuit-b

SNVD brand SV-M301 electric shaver circuit diagram

Small Broadband Antenna Converter

A kind of KV protection circuit

Fresh and hot, aircraft cabin pressure and temperature data recorded by SensorTile.box: [i=s]This post was last edited by littleshrimp on 2020-12-1 11:28[/i]Air pressure data: the air pressure gradually dropped after the plane took off, and gradually rose during landing. I didn't feel an...; littleshrimp ST Sensors & Low Power Wireless Technology Forum

2020 TI Cup Analog Electronic System Design Invitational Competition: ...; gmchen Electronics Design Contest

Qorvo UWB helps Shenzhentong enter the era of smart travel: In recent years, driven by Apple and other manufacturers, the UWB (Ultra Wide Band) market has experienced an explosion. As a competitive communication technology, UWB has the advantages of high posit...; btty038 RF/Wirelessly

Turning off the general interrupt on M16C doesn't seem to work?: I wrote asm("fclr i") in the int2 interrupt subroutine, but I can still enter the interrupt. Have you ever encountered this problem?...; wjbland Renesas Electronics MCUs

What does the outer diameter of the color ring of MULTI-LAYER mean? The size of the drill hole is the inner diameter, so what does the outer diameter mean?: What does the outer diameter of the MULTI-LAYER color ring mean? The blue color ring is the drill hole, and the drill hole size is the inner diameter. The gray color ring is the outer diameter. What d...; 一沙一世 stm32/stm8

What were you doing the day before the college entrance examination? Do you regret choosing this major?: 2019 is almost halfway through, and tomorrow will be the time for many students to become famous. Looking back on my senior year of high school, I was both excited and nervous. I was excited because I...; eric_wang Talking

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components