LTC1750IFW#PBF datasheet, PDF - EEWORLD Datasheet

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LTC1750IFW#PBF: DescriptionIC ADC 14BIT 80MSPS SMPL 48TSSOP; CategoryAnalog mixed-signal IC converter; File Size274KB，20 Pages; ManufacturerLinear ( ADI ); Websitehttp://www.analog.com/cn/index.html; Environmental Compliance

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LTC1750IFW#PBF Overview

IC ADC 14BIT 80MSPS SMPL 48TSSOP

LTC1750IFW#PBF Parametric

Parameter Name	Attribute value
Brand Name	Linear Technology
Is it Rohs certified?	conform to
Maker	Linear ( ADI )
Parts packaging code	TSSOP
package instruction	TSSOP, TSSOP48,.3,20
Contacts	48
Manufacturer packaging code	FW
Reach Compliance Code	compliant
ECCN code	3A991.C.3
Is Samacsys	N
Maximum analog input voltage	1.125 V
Converter type	ADC, PROPRIETARY METHOD
JESD-30 code	R-PDSO-G48
JESD-609 code	e3
length	12.5 mm
Maximum linear error (EL)	0.0183%
Humidity sensitivity level	1
Number of analog input channels	1
Number of digits	14
Number of functions	1
Number of terminals	48
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Output bit code	OFFSET BINARY, 2'S COMPLEMENT BINARY
Output format	PARALLEL, WORD
Package body material	PLASTIC/EPOXY
encapsulated code	TSSOP
Encapsulate equivalent code	TSSOP48,.3,20
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	260
power supply	5 V
Certification status	Not Qualified
Sampling rate	80 MHz
Sample and hold/Track and hold	SAMPLE
Maximum seat height	1.2 mm
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Matte Tin (Sn)
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
width	6.1 mm
Base Number Matches	1

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LTC1750

14-Bit, 80Msps

Wide Bandwidth ADC

DESCRIPTIO

The LTC

1750 is an 80Msps, 14-bit A/D converter de-

signed for digitizing wide dynamic range signals up to

frequencies of 500MHz. The input range of the ADC can be

optimized with the on-chip PGA sample-and-hold circuit

and flexible reference circuitry.

The LTC1750 has a highly linear sample-and-hold circuit

with a bandwidth of 500MHz. The SFDR is 82dB with an

input frequency of 250MHz. Ultralow jitter of 0.12ps

RMS

allows undersampling of IF frequencies with minimal

degradation in SNR. DC specs include

±3LSB

INL and no

missing codes.

The digital interface is compatible with 5V, 3V, 2V and

LVDS logic systems. The ENC and ENC inputs may be

driven differentially from PECL, GTL and other low swing

logic families or from single-ended TTL or CMOS. The low

noise, high gain ENC and ENC inputs may also be driven

by a sinusoidal signal without degrading performance. A

separate output power supply can be operated from 0.5V

to 5V, making it easy to connect directly to any low voltage

DSPs or FIFOs.

The 48-pin TSSOP package with a flow-through pinout

simplifies the board layout.

, LTC and LT are registered trademarks of Linear Technology Corporation.

FEATURES

Sample Rate: 80Msps

500MHz Full Power Bandwidth S/H

Direct IF Sampling Up to 500MHz

PGA Front End (2.25V

P-P

or 1.35V

P-P

Input Range)

75.5dB SNR and 90dB SFDR (PGA = 0)

73dB SNR and 90dB SFDR (PGA = 1)

No Missing Codes

Single 5V Supply

Power Dissipation: 1.45W

Two Pin Selectable Reference Values

Two’s Complement or Offset Binary Outputs

Out-of-Range Indicator

Data Ready Output Clock

Pin-for-Pin Family

48-Pin TSSOP Package

APPLICATIO S

Telecommunications

Receivers

Cellular Base Stations

Spectrum Analysis

Imaging Systems

MRI

Tomography

BLOCK DIAGRA

PGA

IN+

±1.125V

DIFFERENTIAL

–

ANALOG INPUT A

SENSE

80Msps, 14-Bit ADC with a 2.25V Differential Input Range

0.1µF

S/H

CIRCUIT

14-BIT

PIPELINED ADC

CORRECTION

LOGIC AND

SHIFT

OUTPUT

LATCHES

•

D13

CLKOUT

0.5V TO 5V

0.1µF

BUFFER

RANGE

SELECT

1µF

DIFF AMP

GND

CONTROL LOGIC

1750 BD

4.7µF

REF

REFLB

0.1µF

1µF

REFHA

4.7µF

REFLA

REFHB

0.1µF

ENC

1µF

DIFFERENTIAL

ENCODE INPUT

OGND

1µF

MSBINV

1750f

LTC1750IFW#PBF Related Products

	LTC1750IFW#PBF	LTC1750CFW#TR	LTC1750IFW#TR	LTC1750CFW#TRPBF	LTC1750CFW#PBF	LTC1750IFW#TRPBF
Description	IC ADC 14BIT 80MSPS SMPL 48TSSOP	IC adc 14bit 80msps smpl 48tssop	IC adc 14bit 80msps smpl 48tssop	IC ADC 14BIT 80MSPS SMPL 48TSSOP	IC ADC 14BIT 80MSPS SMPL 48TSSOP	IC ADC 14BIT 80MSPS SMPL 48TSSOP
Brand Name	Linear Technology	Linear Technology	Linear Technology	Linear Technology	Linear Technology	Linear Technology
Is it Rohs certified?	conform to	incompatible	incompatible	conform to	conform to	conform to
Maker	Linear ( ADI )	Linear ( ADI )	Linear ( ADI )	Linear ( ADI )	Linear ( ADI )	Linear ( ADI )
Parts packaging code	TSSOP	TSSOP	TSSOP	TSSOP	TSSOP	TSSOP
package instruction	TSSOP, TSSOP48,.3,20	TSSOP,	TSSOP,	TSSOP,	TSSOP, TSSOP48,.3,20	TSSOP,
Contacts	48	48	48	48	48	48
Manufacturer packaging code	FW	FW	FW	FW	FW	FW
Reach Compliance Code	compliant	not_compliant	compliant	compliant	compliant	compliant
ECCN code	3A991.C.3	3A991.C.3	3A991.C.3	3A991.C.3	3A991.C.3	3A991.C.3
Is Samacsys	N	N	N	N	N	N
Converter type	ADC, PROPRIETARY METHOD	ADC, PROPRIETARY METHOD	ADC, PROPRIETARY METHOD	ADC, PROPRIETARY METHOD	ADC, PROPRIETARY METHOD	ADC, PROPRIETARY METHOD
JESD-30 code	R-PDSO-G48	R-PDSO-G48	R-PDSO-G48	R-PDSO-G48	R-PDSO-G48	R-PDSO-G48
JESD-609 code	e3	e0	e0	e3	e3	e3
length	12.5 mm	12.5 mm	12.5 mm	12.5 mm	12.5 mm	12.5 mm
Maximum linear error (EL)	0.0183%	0.0183%	0.0183%	0.0183%	0.0183%	0.0183%
Humidity sensitivity level	1	1	1	1	1	1
Number of analog input channels	1	1	1	1	1	1
Number of digits	14	14	14	14	14	14
Number of functions	1	1	1	1	1	1
Number of terminals	48	48	48	48	48	48
Maximum operating temperature	85 °C	70 °C	85 °C	70 °C	70 °C	85 °C
Output bit code	OFFSET BINARY, 2'S COMPLEMENT BINARY	OFFSET BINARY, 2'S COMPLEMENT BINARY	OFFSET BINARY, 2'S COMPLEMENT BINARY	OFFSET BINARY, 2'S COMPLEMENT BINARY	OFFSET BINARY, 2'S COMPLEMENT BINARY	OFFSET BINARY, 2'S COMPLEMENT BINARY
Output format	PARALLEL, WORD	PARALLEL, WORD	PARALLEL, WORD	PARALLEL, WORD	PARALLEL, WORD	PARALLEL, WORD
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TSSOP	TSSOP	TSSOP	TSSOP	TSSOP	TSSOP
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	260	235	235	260	260	260
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Sampling rate	80 MHz	80 MHz	80 MHz	80 MHz	80 MHz	80 MHz
Sample and hold/Track and hold	SAMPLE	SAMPLE	SAMPLE	SAMPLE	SAMPLE	SAMPLE
Maximum seat height	1.2 mm	1.2 mm	1.2 mm	1.2 mm	1.2 mm	1.2 mm
Nominal supply voltage	5 V	5 V	5 V	5 V	5 V	5 V
surface mount	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	INDUSTRIAL	COMMERCIAL	INDUSTRIAL	COMMERCIAL	COMMERCIAL	INDUSTRIAL
Terminal surface	Matte Tin (Sn)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Matte Tin (Sn)	Matte Tin (Sn)	Matte Tin (Sn)
Terminal form	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING
Terminal pitch	0.5 mm	0.5 mm	0.5 mm	0.5 mm	0.5 mm	0.5 mm
Terminal location	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL
Maximum time at peak reflow temperature	30	20	20	30	30	30
width	6.1 mm	6.1 mm	6.1 mm	6.1 mm	6.1 mm	6.1 mm
Base Number Matches	1	1	1	1	1	1

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