HEF4021B-Q100
8-bit static shift register
Rev. 4 — 21 March 2016
Product data sheet
1. General description
The HEF4021B-Q100 is an 8-bit static shift register (parallel-to-serial converter). It has a
synchronous serial data input (DS), a clock input (CP) and an asynchronous active HIGH
parallel load input (PL). The HEF4021B-Q100 also has eight asynchronous parallel data
inputs (D0 to D7) and buffered parallel outputs from the last three stages (Q5 to Q7). Each
register stage is a D-type master-slave flip-flop with a set direct (SD) and clear direct (CD)
input. Information on D0 to D7 is asynchronously loaded into the register while PL is
HIGH, independent of CP and DS. When PL is LOW, data on DS is shifted into the first
register position. All the data in the register is shifted one position to the right on the
LOW-to-HIGH transition of CP. Schmitt trigger action makes the clock input highly tolerant
of slower rise and fall times. It operates over a recommended V
DD
power supply range of
3 V to 15 V referenced to V
SS
(usually ground). Connect unused inputs must to V
DD
, V
SS
,
or another input. This product has been qualified to the Automotive Electronics Council
(AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from
40 C
to +85
C
and from
40 C
to +125
C
Tolerant of slower rise and fall times
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0
)
Complies with JEDEC standard JESD 13-B
3. Ordering information
Table 1.
Ordering information
All types operate from
40
C to +125
C.
Type number
HEF4021BT-Q100
Package
Name
SO16
Description
plastic small outline package; 16 leads; body width 3.9 mm
Version
SOT109-1
SOT403-1
HEF4021BTT-Q100 TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm
Nexperia
HEF4021B-Q100
8-bit static shift register
5. Pinning information
5.1 Pinning
Fig 3.
Pin configuration
5.2 Pin description
Table 2.
Symbol
Q5 to Q7
D0 to D7
V
SS
PL
CP
DS
V
DD
Pin description
Pin
2, 12, 3
7, 6, 5, 4, 13, 14,15, 1
8
9
10
11
16
Description
buffered parallel output from the last three stages
parallel data input
ground supply voltage
parallel load input
clock input (LOW-to-HIGH edge-triggered)
serial data input
supply voltage
HEF4021B_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 4 — 21 March 2016
3 of 15
Nexperia
HEF4021B-Q100
8-bit static shift register
6. Functional description
Table 3.
Function table
[1]
Outputs
DS
data 1
data 2
data 3
X
X
X
X
X
PL
L
L
L
L
L
L
L
H
Q5
X
X
X
data 1
data 2
data 3
no change
D5
Q6
X
X
X
X
data 1
data 2
no change
D6
Q7
X
X
X
X
X
data 1
no change
D7
Number of clock Inputs
transitions
CP
Serial operation
1
2
3
6
7
8
Parallel operation
X
[1]
H = HIGH voltage level; L = LOW voltage level; X = don’t care;
= LOW to HIGH clock transition; = HIGH to LOW clock transition;
data n = data (HIGH or LOW) on the DS input at the n
th
CP transition.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
DD
I
IK
V
I
I
OK
I
I/O
I
DD
T
stg
T
amb
P
tot
P
[1]
Parameter
supply voltage
input clamping current
input voltage
output clamping current
input/output current
supply current
storage temperature
ambient temperature
total power dissipation
power dissipation
Conditions
V
I
<
0.5
V or V
I
> V
DD
+ 0.5 V
V
O
<
0.5
V or V
O
> V
DD
+ 0.5 V
Min
0.5
-
0.5
-
-
-
65
40
Max
+18
10
10
10
50
+150
+125
500
100
Unit
V
mA
mA
mA
mA
C
C
mW
mW
V
DD
+ 0.5 V
T
amb
40 C
to +125
C
SO16 and TSSOP16 package
per output
[1]
-
-
For SO16 package: P
tot
derates linearly with 8 mW/K above 70
C.
For TSSOP16 package: P
tot
derates linearly with 5.5 mW/K above 60
C.
HEF4021B_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 4 — 21 March 2016
4 of 15
Nexperia
HEF4021B-Q100
8-bit static shift register
8. Recommended operating conditions
Table 5.
Symbol
V
DD
V
I
T
amb
t/V
Recommended operating conditions
Parameter
supply voltage
input voltage
ambient temperature
input transition rise and fall rate
in free air
V
DD
= 5 V
V
DD
= 10 V
V
DD
= 15 V
Conditions
Min
3
0
40
-
-
-
Typ
-
-
-
-
-
-
Max
15
V
DD
+125
3.75
0.5
0.08
Unit
V
V
C
s/V
s/V
s/V
9. Static characteristics
Table 6.
Static characteristics
V
SS
= 0 V; V
I
= V
SS
or V
DD
unless otherwise specified.
Symbol Parameter
V
IH
HIGH-level
input voltage
Conditions
I
O
< 1
A
V
DD
5V
10 V
15 V
V
IL
LOW-level
input voltage
I
O
< 1
A
5V
10 V
15 V
V
OH
HIGH-level
output
voltage
LOW-level
output
voltage
I
O
< 1
A
5V
10 V
15 V
I
O
< 1
A
5V
10 V
15 V
5V
5V
10 V
15 V
5V
10 V
15 V
15 V
5V
10 V
15 V
C
I
input
capacitance
-
T
amb
=
40 C
Min
3.5
7.0
11.0
-
-
-
4.95
9.95
14.95
-
-
-
-
-
-
-
0.64
1.6
4.2
-
-
-
-
-
Max
-
-
-
1.5
3.0
4.0
-
-
-
0.05
0.05
0.05
1.7
0.64
1.6
4.2
-
-
-
0.1
5
10
20
-
T
amb
= 25
C
Min
3.5
7.0
11.0
-
-
-
4.95
9.95
14.95
-
-
-
-
-
-
-
0.5
1.3
3.4
-
-
-
-
-
Max
-
-
-
1.5
3.0
4.0
-
-
-
0.05
0.05
0.05
1.4
0.5
1.3
3.4
-
-
-
0.1
5
10
20
7.5
T
amb
= 85
C
Min
3.5
7.0
11.0
-
-
-
4.95
9.95
14.95
-
-
-
-
-
-
-
0.36
0.9
2.4
-
-
-
-
-
Max
-
-
-
1.5
3.0
4.0
-
-
-
0.05
0.05
0.05
1.1
0.36
0.9
2.4
-
-
-
1.0
150
300
600
-
T
amb
= 125
C
Unit
Min
3.5
7.0
11.0
-
-
-
4.95
9.95
14.95
-
-
-
-
-
-
-
0.36
0.9
2.4
-
-
-
-
-
Max
-
-
-
1.5
3.0
4.0
-
-
-
0.05
0.05
0.05
1.1
0.9
2.4
-
-
-
1.0
150
300
600
-
V
V
V
V
V
V
V
V
V
V
V
V
mA
mA
mA
mA
mA
mA
A
A
A
A
pF
V
OL
I
OH
HIGH-level
V
O
= 2.5 V
output current V = 4.6 V
O
V
O
= 9.5 V
V
O
= 13.5 V
0.36
mA
I
OL
LOW-level
V
O
= 0.4 V
output current V = 0.5 V
O
V
O
= 1.5 V
input leakage V
DD
= 15 V
current
supply
current
I
O
= 0 A
I
I
I
DD
HEF4021B_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 4 — 21 March 2016
5 of 15
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