Latch-Up Current..................................................... >200 mA
Operating Range
Range
Commercial
Ambient
Temperature
[2]
0°C to +70°C
V
CC
5V
±
10%
Electrical Characteristics
Over the Operating Range
Test
Conditions
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
Description
Output HIGH
Voltage
Output LOW
Voltage
Input HIGH
Voltage
Input LOW
Voltage
[1]
Input Load
Current
Output
Leakage
Current
Output Short
Circuit
Current
[3]
V
CC
Operating
Supply
Current
Automatic CE
Power-Down
Current
—TTL Inputs
Automatic CE
Power-Down
Current
—CMOS
Inputs
GND < V
I
< V
CC
GND < V
I
< V
CC
,
Output Disabled
V
CC
= Max.,
V
OUT
= GND
V
CC
= Max.,
I
OUT
= 0 mA,
f = f
MAX
= 1/t
RC
Max. V
CC
,
CE > V
IH
V
IN
> V
IH
or
V
IN
< V
IL
,
f = f
MAX
Max. V
CC
,
CE >
V
CC
– 0.3V, V
IN
>
V
CC
– 0.3V,
or V
IN
< 0.3V, f = 0
V
CC
= Min.,
I
OH
= –4.0 mA
V
CC
= Min.,
I
OL
= 8.0 mA
2.2
–0.5
–1
–1
WCFS1016C1C 12ns
Min.
2.4
0.4
6.0
0.8
+1
+1
2.2
–0.5
–1
–1
Max.
WCFS1016C1C 15ns
Min.
2.4
0.4
6.0
0.8
+1
+1
Max.
Unit
V
V
V
V
µA
µA
I
OS
–300
–300
mA
I
CC
140
130
mA
I
SB1
40
40
mA
I
SB2
10
10
mA
Notes:
1. V
IL
(min.) = –2.0V for pulse durations of less than 20 ns.
2. T
A
is the “Instant On” case temperature.
3. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
Page 2 of 9
WCFS1016C1C
Capacitance
[4]
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz,
V
CC
= 5.0V
Max.
8
8
Unit
pF
pF
AC Test Loads and Waveforms
5V
OUTPUT
30 pF
R 481
Ω
R 481
Ω
5V
OUTPUT
R2
255
Ω
5 pF
INCLUDING
JIG AND
SCOPE
167
30 pF
R2
255
Ω
GND
3.0V
90%
10%
ALL INPUT PULSES
90%
10%
INCLUDING
JIG AND
SCOPE
(a)
OUTPUT
Equivalent to: THÉVENIN
EQUIVALENT
(b)
Rise Time: 1 V/ns
1021B-3
Fall Time:1 V/ns
1.73V
Notes:
4. Tested initially and after any design or process changes that may affect
these parameters
Page 3 of 9
WCFS1016C1C
Switching Characteristics
[5]
Over the Operating Range
WCFS1016C1C 12ns
Parameter
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
DBE
t
LZBE
t
HZBE
WRITE
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
t
BW
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
[6]
OE HIGH to High Z
[6, 7]
WCFS1016C1C 15ns
Min.
15
Max.
Unit
ns
15
3
15
7
0
7
3
7
0
15
7
0
7
15
10
10
0
0
10
8
0
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7
9
ns
ns
Description
Min.
12
Max.
12
3
12
6
0
6
3
6
0
12
6
0
6
12
9
8
0
0
8
6
0
3
6
8
CE LOW to Low Z
[6]
CE HIGH to High Z
[6, 7]
CE LOW to Power-Up
CE HIGH to Power-Down
Byte Enable to Data Valid
Byte Enable to Low Z
Byte Disable to High Z
CYCLE
[8]
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z
[6]
WE LOW to High Z
[6, 7]
Byte Enable to End of Write
Notes:
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the
specified I
OL
/I
OH
and 30-pF load capacitance.
6. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
7. t
HZOE
, t
HZBE
, t
HZCE
, and t
HZWE
are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured
±
500 mV from steady-state voltage.
8. The internal write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE / BLE LOW. CE, WE and BHE / BLE must be LOW to initiate
a write, and the transition of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that
terminates the write.
Page 4 of 9
WCFS1016C1C
Switching Waveforms
Read Cycle No. 1
[9, 10]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled)
ADDRESS
[10, 11]
t
RC
CE
t
ACE
OE
BHE, BLE
t
DOE
t
LZOE
t
DBE
t
LZBE
HIGH IMPEDANCE
t
LZCE
V
CC
SUPPLY
CURRENT
t
PU
50%
t
HZOE
t
HZCE
t
HZBE
DATA VALID
t
PD
50%
IISB
SB
IICC
CC
HIGH
IMPEDANCE
DATA OUT
Notes:
9. Device is continuously selected. OE, CE, BHE and/or BHE = V
IL
.
10. WE is HIGH for read cycle.
11. Address valid prior to or coincident with CE transition LOW.
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