GS8662D06BGD-550 datasheet, PDF

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GS8662D06BGD-550: DescriptionSRAM 1.8 or 1.5V 8M x 8 64M; Categorystorage storage; File Size338KB，33 Pages; ManufacturerGSI Technology; Websitehttp://www.gsitechnology.com/

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GS8662D06BGD-550 Overview

SRAM 1.8 or 1.5V 8M x 8 64M

GS8662D06BGD-550 Parametric

Parameter Name	Attribute value
Maker	GSI Technology
Parts packaging code	BGA
package instruction	13 X 15 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165
Contacts	165
Reach Compliance Code	unknown
ECCN code	3A991.B.2.B
Factory Lead Time	8 weeks
Maximum access time	0.29 ns
Other features	PIPELINED ARCHITECTURE
JESD-30 code	R-PBGA-B165
length	15 mm
memory density	67108864 bit
Memory IC Type	STANDARD SRAM
memory width	8
Number of functions	1
Number of terminals	165
word count	8388608 words
character code	8000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	8MX8
Package body material	PLASTIC/EPOXY
encapsulated code	LBGA
Package shape	RECTANGULAR
Package form	GRID ARRAY, LOW PROFILE
Parallel/Serial	PARALLEL
Certification status	Not Qualified
Maximum seat height	1.4 mm
Maximum supply voltage (Vsup)	1.9 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
width	13 mm

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GS8662D20/38BD-550/500/450/400/350

GS8662D06/11BD-500/450/400/350

165-Bump BGA

Commercial Temp

Industrial Temp

Features

• 2.5 Clock Latency

• Simultaneous Read and Write SigmaQuad™ Interface

• JEDEC-standard pinout and package

• Dual Double Data Rate interface

• Byte Write controls sampled at data-in time

• Burst of 4 Read and Write

• On-Die Termination (ODT) on Data (D), Byte Write (BW),

and Clock (K, K) intputs

• 1.8 V +100/–100 mV core power supply

• 1.5 V or 1.8 V HSTL Interface

• Pipelined read operation

• Fully coherent read and write pipelines

• ZQ pin for programmable output drive strength

• Data Valid Pin (QVLD) Support

• IEEE 1149.1 JTAG-compliant Boundary Scan

• 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package

• RoHS-compliant 165-bump BGA package available

72Mb SigmaQuad-II+

Burst of 4 SRAM

550 MHz–350 MHz

1.8 V V

1.8 V or 1.5 V I/O

SRAMs. The GS8662D06/11/20/38BD SigmaQuad SRAMs

are just one element in a family of low power, low voltage

HSTL I/O SRAMs designed to operate at the speeds needed to

implement economical high performance networking systems.

Clocking and Addressing Schemes

The GS8662D06/11/20/38BD SigmaQuad-II+ SRAMs are

synchronous devices. They employ two input register clock

inputs, K and K. K and K are independent single-ended clock

inputs, not differential inputs to a single differential clock input

buffer.

Each internal read and write operation in a SigmaQuad-II+ B4

RAM is four times wider than the device I/O bus. An input

data bus de-multiplexer is used to accumulate incoming data

before it is simultaneously written to the memory array. An

output data multiplexer is used to capture the data produced

from a single memory array read and then route it to the

appropriate output drivers as needed. Therefore the address

field of a SigmaQuad-II+ B4 RAM is always two address pins

less than the advertised index depth (e.g., the 8M x 8 has a 2M

addressable index).

SigmaQuad-II™ Family Overview

The GS8662D06/11/20/38BD are built in compliance with

the SigmaQuad-II+ SRAM pinout standard for Separate I/O

synchronous SRAMs. They are 75,497,472-bit (72Mb)

Parameter Synopsis (x18/x36)

-550

tKHKH

tKHQV

1.81 ns

0.29ns

-500

2.0 ns

0.33 ns

-450

2.2 ns

0.37 ns

-400

2.5 ns

0.45 ns

-350

2.86 ns

0.45 ns

Parameter Synopsis (x8/x9)

-500

tKHKH

tKHQV

2.0 ns

0.33 ns

-450

2.2 ns

0.37ns

-400

2.5 ns

0.45 ns

-350

2.86 ns

0.45 ns

Rev: 1.02c 8/2017

1/33

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8662D06BGD-550 Related Products

	GS8662D06BGD-550	GS8662D06BD-550I	GS8662D06BD-550	GS8662D11BGD-550	GS8662D11BGD-550I	GS8662D06BGD-550I	GS8662D11BD-550I
Description	SRAM 1.8 or 1.5V 8M x 8 64M	SRAM 1.8 or 1.5V 8M x 8 64M	SRAM 1.8 or 1.5V 8M x 8 64M	SRAM 1.8 or 1.5V 8M x 9 64M	SRAM 1.8 or 1.5V 8M x 9 64M	SRAM 1.8 or 1.5V 8M x 8 64M	Static random access memory 1.8 or 1.5V 8M x 9 64M
Maker	GSI Technology	GSI Technology	GSI Technology	-	-	GSI Technology	GSI Technology
Parts packaging code	BGA	BGA	BGA	-	-	BGA	-
package instruction	13 X 15 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165	13 X 15 MM, 1 MM PITCH, FPBGA-165	13 X 15 MM, 1 MM PITCH, FPBGA-165	-	-	13 X 15 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165	-
Contacts	165	165	165	-	-	165	-
Reach Compliance Code	unknown	unknown	unknown	-	-	unknown	-
ECCN code	3A991.B.2.B	3A991.B.2.B	3A991.B.2.B	-	-	3A991.B.2.B	-
Factory Lead Time	8 weeks	8 weeks	8 weeks	-	-	8 weeks	-
Maximum access time	0.29 ns	0.29 ns	0.29 ns	-	-	0.29 ns	-
Other features	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	-	-	PIPELINED ARCHITECTURE	-
JESD-30 code	R-PBGA-B165	R-PBGA-B165	R-PBGA-B165	-	-	R-PBGA-B165	-
length	15 mm	15 mm	15 mm	-	-	15 mm	-
memory density	67108864 bit	67108864 bit	67108864 bit	-	-	67108864 bit	-
Memory IC Type	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM	-	-	STANDARD SRAM	-
memory width	8	8	8	-	-	8	-
Number of functions	1	1	1	-	-	1	-
Number of terminals	165	165	165	-	-	165	-
word count	8388608 words	8388608 words	8388608 words	-	-	8388608 words	-
character code	8000000	8000000	8000000	-	-	8000000	-
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	-	-	SYNCHRONOUS	-
Maximum operating temperature	70 °C	85 °C	70 °C	-	-	85 °C	+ 85 C
organize	8MX8	8MX8	8MX8	-	-	8MX8	8 M x 9
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	-	-	PLASTIC/EPOXY	-
encapsulated code	LBGA	LBGA	LBGA	-	-	LBGA	-
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	-	-	RECTANGULAR	-
Package form	GRID ARRAY, LOW PROFILE	GRID ARRAY, LOW PROFILE	GRID ARRAY, LOW PROFILE	-	-	GRID ARRAY, LOW PROFILE	-
Parallel/Serial	PARALLEL	PARALLEL	PARALLEL	-	-	PARALLEL	-
Certification status	Not Qualified	Not Qualified	Not Qualified	-	-	Not Qualified	-
Maximum seat height	1.4 mm	1.4 mm	1.4 mm	-	-	1.4 mm	-
Maximum supply voltage (Vsup)	1.9 V	1.9 V	1.9 V	-	-	1.9 V	-
Minimum supply voltage (Vsup)	1.7 V	1.7 V	1.7 V	-	-	1.7 V	-
Nominal supply voltage (Vsup)	1.8 V	1.8 V	1.8 V	-	-	1.8 V	-
surface mount	YES	YES	YES	-	-	YES	-
technology	CMOS	CMOS	CMOS	-	-	CMOS	-
Temperature level	COMMERCIAL	INDUSTRIAL	COMMERCIAL	-	-	INDUSTRIAL	-
Terminal form	BALL	BALL	BALL	-	-	BALL	-
Terminal pitch	1 mm	1 mm	1 mm	-	-	1 mm	-
Terminal location	BOTTOM	BOTTOM	BOTTOM	-	-	BOTTOM	-
width	13 mm	13 mm	13 mm	-	-	13 mm	-

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