1:5, Differential-to-3.3V LVPECL Zero
Delay Clock Generator
Data Sheet
8735-31
General Description
The 8735-31 is a highly versatile 1:5 Differential -to-3.3V LVPECL
Clock Generator. The 8735-31 has a fully integrated PLL and can
be configured as zero delay buffer, multiplier or divider, and has an
output frequency range of 15.625MHz to 350MHz. The reference
divider, feedback divider and output divider are each
programmable, thereby allowing for the following output-to-input
frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. The external
feedback allows the device to achieve “zero delay” between the
input clock and the output clocks. The PLL_SEL pin can be used
to bypass the PLL for system test and debug purposes. In bypass
mode, the reference clock is routed around the PLL and into the
internal output dividers.
Features
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Five differential 3.3V LVPECL output pairs
Selectable differential clock inputs
CLKx/nCLKx pairs can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
Output frequency range: 15.625MHz to 350MHz
Input frequency range: 15.625MHz to 350MHz
VCO range: 250MHz to 700MHz
External feedback for “zero delay” clock regeneration
with configurable frequencies
Programmable dividers allow for the following output-to-input
frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
Cycle-to-cycle jitter: 60ps (maximum)
Output skew: 35ps (maximum)
Static phase offset: 55ps ± 125ps
Full 3.3V supply voltage
0°C to 70°C ambient operating temperature
Available in lead-free (RoHS 6) package
Block Diagram
Q0
PLL_SEL
Pullup
÷2, ÷4, ÷8, ÷16,
÷32
,
÷64, ÷128
0
1
1
0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
8:1, 4:1, 2:1, 1:1,
1:2, 1:4, 1:8
Pin Assignment
PLL_SEL
SEL3
V
CCA
V
CCO
V
EE
Q4
nQ4
V
CC
32 31 30 29 28 27 26 25
SEL0
SEL1
CLK0
nCLK0
CLK1
nCLK1
CLK_SEL
MR
1
2
3
4
5
6
7
8
9
V
CC
CLK0
Pulldown
nCLK0
Pullup
nCLK1
CLK1
Pulldown
Pullup
24
23
22
21
20
19
18
17
10 11 12 13 14 15 16
nFB_IN
FB_IN
SEL2
V
CCO
nQ0
V
EE
Q0
V
CCO
Q3
nQ3
Q2
nQ2
Q1
nQ1
V
CCO
PLL
CLK_SEL
Pulldown
FB_IN
Pulldown
nFB_IN
Pullup
SEL0
Pulldown
SEL1
Pulldown
SEL2
Pulldown
SEL3
Pulldown
MR
Pulldown
8735-31
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
©2016 Integrated Device Technology, Inc
1
Revision B January 27, 2016
8735-31 Data Sheet
Table 1. Pin Descriptions
Number
1, 2,
12, 29
3
4
5
6
7
Name
SEL0, SEL1,
SEL2, SEL3
CLK0
nCLK0
CLK1
nCLK1
CLK_SEL
Input
Input
Input
Input
Input
Input
Type
Pulldown
Pulldown
Pullup
Pulldown
Pullup
Pulldown
Description
Determines output divider values in Table 3.
LVCMOS / LVTTL interface levels.
Non-inverting differential clock input.
Inverting differential clock input.
Non-inverting differential clock input.
Inverting differential clock input.
Clock select input. When HIGH, selects CLK1/nCLK1. When LOW, selects
CLK0/nCLK0. LVCMOS / LVTTL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
causing the true outputs Qx to go low and the inverted outputs nQx to go high.
When logic LOW, the internal dividers and the outputs are enabled.
LVCMOS / LVTTL interface levels.
Core supply pins.
Pullup
Inverting differential feedback input to phase detector for regenerating clocks
with “zero delay.”
Non-inverted differential feedback input to phase detector for regenerating
clocks with
“zero delay.”
Negative supply pins.
Differential output pair. LVPECL interface levels.
Output supply pins.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels..
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Analog supply pin.
Pullup
PLL select. Selects between the PLL and reference clock as the input to the
dividers. When LOW, selects reference clock. When HIGH, selects PLL.
LVCMOS/LVTTL interface levels.
8
MR
Input
Pulldown
9, 32
10
V
CC
nFB_IN
Power
Input
11
13, 28
14, 15
16, 17, 24, 25
18, 19
20, 21
22, 23
26, 27
30
31
FB_IN
V
EE
nQ0, Q0
V
CCO
nQ1, Q1
nQ2, Q2
nQ3, Q3
nQ4, Q4
V
CCA
PLL_SEL
Input
Power
Output
Power
Output
Output
Output
Output
Power
Input
Pulldown
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
k
k
©2016 Integrated Device Technology, Inc
2
Revision B January 27, 2016
8735-31 Data Sheet
Function Tables
Table 3A. Control Input Function Table
Inputs
Outputs
PLL_SEL = 1
PLL Enable Mode
Reference Frequency Range (MHz)
125 - 350
62.5 - 175
31.25 - 87.5
15.625 - 43.75
125 - 350
62.5 - 175
31.25 - 87.5
125 - 350
62.5 - 175
125 - 350
62.5 - 175
31.25 - 87.5
15.625 - 43.75
31.25 - 87.5
15.625 - 43.75
15.625 - 43.75
Q0:Q4, nQ0:nQ4
÷1
÷1
÷1
÷1
÷2
÷2
÷2
÷4
÷4
÷8
x2
x2
x2
x4
x4
x8
SEL3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
SEL2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
SEL1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
SEL0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
©2016 Integrated Device Technology, Inc
3
Revision B January 27, 2016
8735-31 Data Sheet
Table 3B. PLL Bypass Function Table
Inputs
Outputs
PLL_SEL = 0
PLL Bypass Mode
SEL1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
SEL0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Q0:Q4, nQ0:nQ4
÷8
÷8
÷8
÷16
÷16
÷16
÷32
÷32
÷64
÷128
÷4
÷4
÷8
÷2
÷4
÷2
SEL3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
SEL2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
©2016 Integrated Device Technology, Inc
4
Revision B January 27, 2016
8735-31 Data Sheet
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
Continuos Current
Surge Current
Package Thermal Impedance,
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
CC
+ 0.5V
50mA
100mA
47.9C/W (0 lfpm)
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
CC
= V
CCA
= V
CCO
= 3.3V ± 5%, V
EE
= 0V, T
A
= 0°C to 70°C
Symbol
V
CC
V
CCA
V
CCO
I
EE
I
CCA
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
3.135
3.135
3.135
Typical
3.3
3.3
3.3
Maximum
3.465
3.465
3.465
150
15
Units
V
V
V
mA
mA
Table 4B. LVCMOS/LVTTL DC Characteristics,
V
CC
= V
CCA
= V
CCO
= 3.3V ± 5%, V
EE
= 0V, T
A
= 0°C to 70°C
Symbol
V
IH
V
IL
I
IH
Parameter
Input High Voltage
Input Low Voltage
CLK_SEL,
SEL[0:3], MR
PLL_SEL
CLK_SEL,
SEL[0:3], MR
PLL_SEL
V
CC
= V
IN
= 3.465V
V
CC
= V
IN
= 3.465V
V
CC
= 3.465V, V
IN
= 0V
V
CC
= 3.465V, V
IN
= 0V
-5
-150
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
CC
+ 0.3
0.8
150
5
Units
V
V
µA
µA
µA
µA
Input High Current
I
IL
Input Low Current
©2016 Integrated Device Technology, Inc
5
Revision B January 27, 2016
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