January 2007
HYS64T32x00EDL–[25F/…/3.7]–B2
HYS64T64x20EDL–[25F/…/3.7]–B2
HYS64T128x21EDL–[25F/…/3.7]B2
200-Pin SO-DIMM DDR2 SDRAM Modules
DDR2 SDRAM
RoHs Compliant Products
Internet Data Sheet
Rev. 1.1
Internet Data Sheet
HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2
Small Outlined DDR2 SDRAM Modules
HYS64T32x00EDL–[25F/…/3.7]–B2, HYS64T64x20EDL–[25F/…/3.7]–B2, HYS64T128x21EDL–[25F/…/3.7]B2
Revision History: 2007-01, Rev. 1.1
Page
All
All
4
Subjects (major changes since last revision)
Adapted internet edition
Updated HYS64T[32/64/128]9xxEDL–[25F/.../3.7](–)B2
Table 2 corrected product string to 21 digits
Previous Revision: 2006-10, Rev. 1.0
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qag_techdoc_rev400 / 3.2 QAG / 2006-08-07
08212006-PKYN-2H1B
2
Internet Data Sheet
HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2
Small Outlined DDR2 SDRAM Modules
1
Overview
This chapter gives an overview of the 200-Pin SO-DIMM DDR2 SDRAM Modules product family and describes its main
characteristics.
1.1
Features
•
•
•
•
•
•
•
•
•
•
Programmable self refresh rate via EMRS2 setting
Programmable partial array refresh via EMRS2 settings
DCC enabling via EMRS2 setting
All speed grades faster than DDR2–400 comply with
DDR2–400 timing specifications.
All inputs and outputs SSTL_1.8 compatible
Off-Chip Driver Impedance Adjustment (OCD) and On-Die
Termination (ODT)
Serial Presence Detect with E
2
PROM
SO-DIMM Dimensions (nominal): 30 mm high,
67.60 mm wide
Based on standard reference layouts Raw Card “A”,
“C”,”E”
RoHS compliant products
1)
• 200-Pin PC2–6400, PC2–5300 and PC2–4200 DDR2
SDRAM memory modules for use as main memory when
installed in systems such as mobile personal computers.
• 32M
×
64, 64M
×
64 and 128M
×
64 module
organization,and 32M
×
16, 64M
×
8 chip organization
• Standard Double-Data-Rate-Two Synchronous DRAMs
(DDR2 SDRAM) with a single + 1.8 V (± 0.1 V) power
supply
• 256MB, 512MB and 1GB modules built with 512-Mbit
DDR2 SDRAMs in PG-TFBGA-60 and PG-TFBGA-84
chipsize packages
• Programmable CAS Latencies (3, 4 ,5 and 6), Burst
Length (8 & 4) and Burst Type
• Auto Refresh (CBR) and Self Refresh
TABLE 1
Performance Table
Product Type Speed Code
Speed Grade
Max. Clock Frequency
@CL6
@CL5
@CL4
@CL3
Min. RAS-CAS-Delay
Min. Row Precharge Time
Min. Row Active Time
Min. Row Cycle Time
–2.5F
PC2–6400
5–5–5
–2.5
PC2–6400
6–6–6
400
333
266
200
15
15
45
60
–3
PC2–5300
4–4–4
—
333
333
200
12
12
45
57
–3S
PC2–5300
5–5–5
—
333
266
200
15
15
45
60
–3.7
PC2–4200
4–4–4
—
266
266
200
15
15
45
60
Unit
—
MHz
MHz
MHz
MHz
ns
ns
ns
ns
f
CK6
f
CK5
f
CK4
f
CK3
t
RCD
t
RP
t
RAS
t
RC
400
400
266
200
12.5
12.5
45
57.5
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
Rev. 1.1, 2007-01
08212006-PKYN-2H1B
3
Internet Data Sheet
HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2
Small Outlined DDR2 SDRAM Modules
1.2
Description
capacitors are mounted on the PCB board. The DIMMs
feature serial presence detect based on a serial E
2
PROM
device using the 2-pin I
2
C protocol. The first 128 bytes are
programmed with configuration data and are write protected;
the second 128 bytes are available to the customer.
The Qimonda HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2
module family are small outline DIMM modules “SO-DIMMs”
with 30 mm height based on DDR2 technology. DIMMs are
available as non-ECC modules in 32M
×
64 (256 MB),
64M
×
64 (512 MB) and 128M
×
64 (1 GB) organization and
density, intended for mounting into 200-pin connector
sockets.
The memory array is designed with 512-Mbit Double-Data-
Rate-Two (DDR2) Synchronous DRAMs. Decoupling
TABLE 2
Ordering Information for RoHS Compliant Products
Product Type
1)
PC2–6400
HYS64T32000EDL–25F–B2
HYS64T32900EDL–25F–B2
HYS64T64020EDL–25F–B2
HYS64T64920EDL–25F–B2
HYS64T128021EDL–25FB2
HYS64T128921EDL–25FB2
PC2–6400
HYS64T32000EDL–2.5–B2
HYS64T32900EDL–2.5–B2
HYS64T64020EDL–2.5–B2
HYS64T64920EDL–2.5–B2
HYS64T128021EDL–2.5B2
HYS64T128921EDL–2.5B2
PC2–5300
HYS64T32000EDL–3–B2
HYS64T32900EDL–3–B2
HYS64T64020EDL–3–B2
HYS64T64920EDL–3–B2
HYS64T128021EDL–3–B2
HYS64T128921EDL–3–B2
PC2–5300
HYS64T32000EDL–3S–B2
HYS64T32900EDL–3S–B2
HYS64T64020EDL–3S–B2
HYS64T64920EDL–3S–B2
HYS64T128021EDL–3S–B2
HYS64T128921EDL–3S–B2
256 MB 1R
×
16 PC2–5300S–555–12–C0
512 MB 2R
×
16 PC2–5300S–555–12–A0
1 GB 2R
×
8 PC2-5300S–555–12–E0
1 Rank, Non-ECC
2 Rank, Non-ECC
2 Rank, Non-ECC
512 Mbit (×16)
512 Mbit (×16)
512 Mbit (×8)
256 MB 1R
×
16 PC2–5300S–444–12–C0
512 MB 2R
×
16 PC2–5300S–444–12–A0
1 GB 2R
×
8 PC2-5300S–444–12–E0
1 Rank, Non-ECC
2 Rank, Non-ECC
2 Rank, Non-ECC
512 Mbit (×16)
512 Mbit (×16)
512 Mbit (×8)
256 MB 1R
×
16 PC2–6400S–666–12–C0
512 MB 2R
×
16 PC2–6400S–666–12–A0
1 GB 2R
×
8 PC2-6400S–666–12–E0
1 Rank, Non-ECC
2 Rank, Non-ECC
2 Rank, Non-ECC
512 Mbit (×16)
512 Mbit (×16)
512 Mbit (×8)
256 MB 1R
×
16 PC2–6400S–555–12–C0
512 MB 2R
×
16 PC2–6400S–555–12–A0
1 GB 2R
×
8 PC2-6400S–555–12–E0
1 Rank, Non-ECC
2 Rank, Non-ECC
2 Rank, Non-ECC
512 Mbit (×16)
512 Mbit (×16)
512 Mbit (×8)
Compliance Code
2)
Description
SDRAM
Technology
Rev. 1.1, 2007-01
08212006-PKYN-2H1B
4
Internet Data Sheet
HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2
Small Outlined DDR2 SDRAM Modules
Product Type
1)
PC2–4200
HYS64T32000EDL–3.7–B2
HYS64T32900EDL–3.7–B2
HYS64T64020EDL–3.7–B2
HYS64T64920EDL–3.7–B2
HYS64T128021EDL–3.7B2
HYS64T128921EDL–3.7B2
Compliance Code
2)
Description
SDRAM
Technology
512 Mbit (×16)
512 Mbit (×16)
512 Mbit (×8)
256 MB 1R
×
16 PC2–4200S–444–12–C0
512 MB 2R
×
16 PC2–4200S–444–12–A0
1 GB 2R
×
8 PC2-4200S–444–12–E0
1 Rank, Non-ECC
2 Rank, Non-ECC
2 Rank, Non-ECC
1) All Product Type numbers end with a place code, designating the silicon die revision. Example: HYS64T64020EDL–3.7–B2, indicating
Rev. “B” dies are used for DDR2 SDRAM components. For all Qimonda DDR2 module and component nomenclature see
Chapter 6
of
this data sheet.
2) The Compliance Code is printed on the module label and describes the speed grade, for example “PC2–4200S–444–12–A0”, where
4200S means Small Outlined Unbuffered DIMM modules with 4.26 GB/sec Module Bandwidth and “444-12” means Column Address
Strobe (CAS) latency = 4, Row Column Delay (RCD) latency = 4 and Row Precharge (RP) latency = 4 using the latest JEDEC SPD
Revision 1.2 and produced on the Raw Card “A”.
TABLE 3
Address Format
DIMM
Density
256 MByte
512 MByte
1 GByte
Module
Organization
32M
×
64
64M
×
64
128M
×
64
Memory
Ranks
1
2
2
ECC/
Non-ECC
Non-ECC
Non-ECC
Non-ECC
# of SDRAMs # of row/bank/column
bits
4
8
16
13/2/10
13/2/10
14/2/10
Raw
Card
C
A
E
TABLE 4
Components on Modules
Product Type
1)2)
HYS64T32000EDL
HYS64T32900EDL
HYS64T64020EDL
HYS64T64920EDL
HYS64T128021EDL
HYS64T128921EDL
DRAM Components
2)
HYB18T512160B2F
HYB18T512160B2F
HYB18T512800B2F
DRAM Density
512 Mbit
512 Mbit
512 Mbit
DRAM Organisation
32M
×
16
32M
×
16
64M
×
8
1) For a detailed description of all functionalities of the DRAM components on these modules see the component data sheet.
2) Green Product
Rev. 1.1, 2007-01
08212006-PKYN-2H1B
5
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