IC41C82052S
IC41LV82052S
2M x 8 (16-MBIT) DYNAMIC
RAM
WITH .AST PAGE MODE
.EATURES
.AST Page Mode access cycle
TTL compatible inputs and outputs
Refresh Interval:
Refresh Mode:
4)5-Only,
+)5-before-4)5
(CBR), and Hidden,
2,048 cycles/32 ms
Self refresh Mode 2,048 cycles/128 ms
JEDEC standard pinout
Single power supply:
5V±10% or 3.3V ± 10%
Byte Write and Byte Read operation via
+)5
DESCRIPTION
The
1+51
82052S Series is a 2,097,152 x 8-bit high-perfor-
mance CMOS Dynamic Random Access Memory. The .ast
Page Mode allows 2,048 random accesses within a single row
with access cycle time as short as 20 ns per 8-bit word.
These features make the 82052S Series ideally suited for high-
bandwidth graphics, digital signal processing, high-performance
computing systems, and peripheral applications.
The 82052S Series is packaged in a 28-pin 300mil SOJ and a
28 pin TSOP-2
PRODUCT SERIES OVERVIEW
Part No.
IC41C82052S
IC41LV82052S
Refresh
2K
2K
Voltage
5V ± 10%
3.3V ± 10%
KEY TIMING PARAMETERS
Parameter
RAS
Access Time (t
RAC
)
CAS
Access Time (t
CAC
)
Column Address Access Time (t
AA
)
EDO Page Mode Cycle Time (t
PC
)
Read/Write Cycle Time (t
RC
)
-50
50
13
25
20
84
-60
60
15
30
25
104
Unit
ns
ns
ns
ns
ns
PIN CON.IGURATION
28 Pin SOJ, TSOP-2
VCC
I/O0
I/O1
I/O2
I/O3
WE
RAS
NC
A10
A0
A1
A2
A3
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
GND
I/O7
I/O6
I/O5
I/O4
CAS
OE
A9
A8
A7
A6
A5
A4
GND
PIN DESCRIPTIONS
A0-A10
I/O0-7
WE
OE
RAS
CAS
Vcc
GND
NC
Address Inputs
Data Inputs/Outputs
Write Enable
Output Enable
Row Address Strobe
Column Address Strobe
Power
Ground
No Connection
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
Integrated Circuit Solution Inc.
DR016-0A 06/12/2001
1
IC41C82052S
IC41LV82052S
.unctional Description
The IC41C82052S and IC41LV82052S are CMOS DRAMs
optimized for high-speed bandwidth, low power
applications. During READ or WRITE cycles, each bit is
uniquely addressed through the 11 address bits. These
are entered 11 bits (A0-A10) at a time for the 2K refresh
device. The row address is latched by the Row Address
Strobe (RAS). The column address is latched by the
Column Address Strobe (CAS).
RAS
is used to latch the
first nine bits and
CAS
is used the latter ten bits.
Refresh Cycle
To retain data, 2,048 refresh cycles are required in each
32 ms period. There are two ways to refresh the memory:
1. By clocking each of the 2,048 row addresses (A0
through A10) with RAS at least once every 32 ms. Any
read, write, read-modify-write or RAS-only cycle re-
freshes the addressed row.
2. Using a
CAS-before-RAS
refresh cycle.
CAS-before-
RAS
refresh is activated by the falling edge of
RAS,
while holding
CAS
LOW. In
CAS-before-RAS
refresh
cycle, an internal 11-bit counter provides the row ad-
dresses and the external address inputs are ignored.
CAS-before-RAS
is a refresh-only mode and no data
access or device selection is allowed. Thus, the output
remains in the High-Z state during the cycle.
Memory Cycle
A memory cycle is initiated by bring
RAS
LOW and it is
terminated by returning both
RAS
and
CAS
HIGH. To
ensures proper device operation and data integrity any
memory cycle, once initiated, must not be ended or
aborted before the minimum t
RAS
time has expired. A new
cycle must not be initiated until the minimum precharge
time t
RP
, t
CP
has elapsed.
Self Refresh Cycle
The Self Refresh allows the user a dynamic refresh, data
retention mode at the extended refresh period of 128 ms.
i.e., 62.5 µs per row when using distributed CBR refreshes.
The feature also allows the user the choice of a fully static,
low power data retention mode. The optional Self Refresh
feature is initiated by performing a CBR Refresh cycle and
holding
RAS
LOW for the specified t
RAS
.
The Self Refresh mode is terminated by driving
RAS
HIGH
for a minimum time of t
RP
. This delay allows for the
completion of any internal refresh cycles that may be in
process at the time of the
RAS
LOW-to-HIGH transition. If
the DRAM controller uses a distributed refresh sequence,
a burst refresh is not required upon exiting Self Refresh.
However, if the DRAM controller utilizes a
RAS-only
or
burst refresh sequence, all 2,048 rows must be refreshed
within the average internal refresh rate, prior to the re-
sumption of normal operation.
Read Cycle
A read cycle is initiated by the falling edge of
CAS
or
OE,
whichever occurs last, while holding
WE
HIGH. The
column address must be held for a minimum time specified
by t
AR
. Data Out becomes valid only when t
RAC
, t
AA
, t
CAC
and t
OEA
are all satisfied. As a result, the access time is
dependent on the timing relationships between these
parameters.
Write Cycle
A write cycle is initiated by the falling edge of
CAS
and
WE,
whichever occurs last. The input data must be valid at or
before the falling edge of
CAS
or
WE,
whichever occurs
last.
Power-On
After application of the V
CC
supply, an initial pause of
200 µs is required followed by a minimum of eight initial-
ization cycles (any combination of cycles containing a
RAS
signal).
During power-on, it is recommended that
RAS
track with
V
CC
or be held at a valid V
IH
to avoid current surges.
Integrated Circuit Solution Inc.
DR016-0A 06/12/2001
3
IC41C82052S
IC41LV82052S
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
T
V
CC
I
OUT
P
D
T
A
T
STG
Parameters
Voltage on Any Pin Relative to GND
Supply Voltage
Output Current
Power Dissipation
Commercial Operation Temperature
Storage Temperature
5V
3.3V
5V
3.3V
Rating
1.0 to +7.0
0.5 to +4.6
1.0 to +7.0
0.5 to +4.6
50
1
0 to +70
55 to +125
Unit
V
V
mA
W
°C
°C
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
RECOMMENDED OPERATING CONDITIONS
(Voltages are referenced to GND.)
Symbol
V
CC
V
IH
V
IL
T
A
Parameter
Supply Voltage
Input High Voltage
Input Low Voltage
Commercial Ambient Temperature
5V
3.3V
5V
3.3V
5V
3.3V
Min.
4.5
3.0
2.4
2.0
1.0
0.3
0
Typ.
5.0
3.3
Max.
5.5
3.6
V
CC
+ 1.0
V
CC
+ 0.3
0.8
0.8
70
Unit
V
V
V
°C
CAPACITANCE
(1,2)
Symbol
C
IN
1
C
IN
2
C
IO
Parameter
Input Capacitance: A0-A10
Input Capacitance:
RAS, CAS, WE, OE
Data Input/Output Capacitance: I/O0-I/O7
Max.
5
7
7
Unit
p.
p.
p.
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T
A
= 25°C, f = 1 MHz.
4
Integrated Circuit Solution Inc.
DR016-0A 06/12/2001
IC41C82052S
IC41LV82052S
ELECTRICAL CHARACTERISTICS
(1)
(Recommended Operating Conditions unless otherwise noted.)
Symbol
I
IL
I
IO
V
OH
V
OL
I
CC
1
I
CC
2
I
CC
3
Parameter
Input Leakage Current
Output Leakage Current
Output High Voltage Level
Output Low Voltage Level
Standby Current: TTL
Standby Current: CMOS
Operating Current:
Random Read/Write
(2,3,4)
Average Power Supply Current
Operating Current:
.ast Page Mode
(2,3,4)
Average Power Supply Current
Refresh Current:
RAS-Only
(2,3)
Average Power Supply Current
Refresh Current:
CBR
(2,3,5)
Average Power Supply Current
Self Refrsh Current
Test Condition
Any input 0V < V
IN
< Vcc
Other inputs not under test = 0V
Output is disabled (Hi-Z)
0V < V
OUT
< Vcc
I
OH
= 5.0 mA with V
CC
=5V
I
OH
= 2.0 mA with V
CC
=3.3V
I
OL
= 4.2 mA with V
CC
=5V
I
OL
= 2 mA with V
CC
=3.3V
RAS, CAS
> V
IH
RAS, CAS
> V
CC
0.2V
RAS, CAS,
Address Cycling, t
RC
= t
RC
(min.)
RAS
= V
IL
,
CAS,
t
RC
= t
RC
(min.)
RAS
Cycling,
CAS
> V
IH
t
RC
= t
RC
(min.)
RAS, CAS
Cycling
t
RC
= t
RC
(min.)
Self Refresh Mode
5V
3.3V
5V
3.3V
-50
-60
-50
-60
-50
-60
-50
-60
5V
3.3V
Speed
Min.
5
5
2.4
Max.
5
5
0.4
2
0.5
1
0.5
120
110
90
80
120
110
120
110
400
300
Unit
µA
µA
V
V
mA
mA
mA
I
CC
4
mA
I
CC
5
mA
I
CC
6
mA
Iccs
µA
µA
Notes:
1. An initial pause of 200 µs is required after power-up followed by eight
RAS
refresh cycles (RAS-Only or CBR) before proper device
operation is assured. The eight
RAS
cycles wake-up should be repeated any time the t
RE.
refresh requirement is exceeded.
2. Dependent on cycle rates.
3. Specified values are obtained with minimum cycle time and the output open.
4. Column-address is changed once each EDO page cycle.
5. Enables on-chip refresh and address counters.
Integrated Circuit Solution Inc.
DR016-0A 06/12/2001
5
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