The data of STM32 ADC is tampered when using DMA mode

littleshrimp

The data of STM32 ADC is tampered when using DMA mode [Copy link]

 

During the recent test, it was found that the data read by STM32 ADC using DMA mode would appear as follows

I started to suspect that it was high-frequency interference from external signals. After a few days of testing, I found that this was actually extra data inserted into the memory data output by DMA.

It can be seen clearly from the second picture that the waveform will become normal after removing the "high frequency" signal in the middle

Therefore, the "high frequency" signal is an extra part, not a superposition of the original signal.

There is another very strange problem. This part of the extra data has some connection with the actual signal. If you look closely, it seems to be the same as the original signal after low-pass filtering.

This phenomenon does not occur often. I found that when outputting a sinusoidal signal with a relatively small amplitude, and making the zero crossing point of this sinusoidal signal at vref/2 (2048 CODE of 12-bit ADC), this situation will occur. The sampling rate of the ADC or whether the ADC uses an amplifier buffer will make the results different.

I have tried STM32G474 and STM32L452 and both have this problem. However, sometimes the phenomenon is not so obvious when the sampling rate is lowered, or this phenomenon is not seen

I have tried STM32F413 and have never seen this phenomenon.

If you are interested, you can try it. Using the STM32's own DAC can generate this signal.

stm32g474 test project, A2 is DAC output, A0 is ADC input, just connect A0 and A4 with a route

g474.rar (9.77 MB, downloads: 16)

2019-9-15 13:43 上传

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This is the data collected several times

adc数据分析2.xlsx (848.05 KB, downloads: 5)

2019-9-15 13:46 上传

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If you know the solution or the manufacturer's technical support, please help me. This problem has troubled me for many days. Thank you.

huo_hu

What about changing the frequency?

littleshrimp

huo_hu posted on 2019-9-15 14:27 What about changing the frequency

Are you talking about the sampling rate? If you lower it to a very low level, you won't see this phenomenon. If you only lower the inserted data, there will be a change, but it still exists.

huo_hu

Now the computer has no software installed. I suspect that there is something wrong with your DMA configuration. Is it caused by DMA discontinuity?

wenyangzeng

It seems that the problem lies with the signal source rather than the ADC itself. The data of the DAC array in the official DAC demo file of ST itself is problematic.

littleshrimp

huo_hu posted on 2019-9-15 14:47 Now the computer has no software installed. I suspect that there is a problem with your DMA configuration. Is it caused by DMA discontinuity?

It should not be a DMA configuration problem

littleshrimp

wenyangzeng published on 2019-9-15 20:23 It seems that the problem is with the signal source rather than the ADC itself. The data of the DAC array in the official DAC demo file of ST itself is problematic.

I have measured it with an oscilloscope and it is not a problem with the signal source.

littleshrimp

In this project I used the internal RC oscillator, but the problem disappeared when I changed the clock source to an external crystal oscillator.

However, careful testing found that similar problems still exist, but they are not obvious.

The picture below is a subsequent test, using 2 ADCs, 170MHz main frequency, ADC clock 42.5MHz, 2.5MSPS sampling rate

Increasing the main frequency and reducing the sampling rate can alleviate the problem, but the problem still exists

viphotman

Have you tried STM32F103?

huo_hu

littleshrimp posted on 2019-9-16 08:56 In this project, I used the internal RC oscillator. The problem disappeared when the clock source was changed to an external crystal oscillator. However, after careful testing, I found that similar problems still exist. I just...

F4 has the problem of internal RC instability, try not to use it, and it has been found to have problems before

huo_hu

When you change the frequency of the signal source, does the problematic data point remain fixed in phase?

littleshrimp

huo_hu published on 2019-9-16 12:53 When you change the frequency of the signal source, does the data point with the problem remain fixed in phase?

The problem usually occurs at 2048 of the adc code. Adjusting the DC bias of the signal source changes the phase. When the signal swing does not pass 2048, there will be no problem.

jackfrost

It's a bit scary that DMA tampered with data. ST should not make such low-level errors. It's always around 2048, which makes me think. It reminds me that some RRIO op amps are distorted because they switch back and forth at the critical point of the NPN PNP input stage architecture under certain voltage levels. If your ADC DAC uses built-in op amps or buffers, the built-in op amps also have power consumption mode settings. However, I don't believe that ST's hardware has such a serious defect. It's probably better to look for the cause externally. I'm drawing the H750VB board these days. It has been delayed for a year. I want to finish it before National Day to see its 16BIT ADC performance. After the board is drawn, I will try my 474

littleshrimp

jackfrost posted on 2019-9-19 09:21 DMA tampering with data is a bit scary. ST should not make such low-level mistakes. It is always around 2048, which makes people think about it. I think of a certain...

The reason for data tampering was found to be a clock problem, but the specific reason for this is not clear.

The small signal is not smooth because VREFBUF is set to Disable. The problem is solved after setting it to external reference voltage. I don't know why this happens.

niaonnn

I recently debugged DMA to read multi-channel ADC and found that the data was very unstable. When I directly used ADC to read the data, it was very stable. I wonder if it is the same reason as yours. Did you change the external clock?

littleshrimp

niaonnn posted on 2019-11-4 10:25 I recently debugged DMA to read multi-channel ADC and found that the data was very unstable. The data I read directly with ADC was very stable. I don’t know if it’s because...

It works well.

littleshrimp

niaonnn posted on 2019-11-4 10:25 I recently debugged DMA to read multi-channel ADC and found that the data was very unstable. The data I read directly with ADC was very stable. I don’t know if it’s...