FPGA - Field Programmable Gate Array 1200 LUTs 211 I/O 1.2V -3 SPD
Parameter Name | Attribute value |
Is it lead-free? | Contains lead |
Is it Rohs certified? | incompatible |
Maker | Lattice |
Parts packaging code | BGA |
package instruction | CABGA-256 |
Contacts | 256 |
Reach Compliance Code | unknown |
ECCN code | EAR99 |
maximum clock frequency | 420 MHz |
JESD-30 code | S-PBGA-B256 |
JESD-609 code | e0 |
length | 14 mm |
Humidity sensitivity level | 3 |
Dedicated input times | 7 |
Number of I/O lines | 211 |
Number of entries | 211 |
Number of logical units | 1200 |
Output times | 211 |
Number of terminals | 256 |
Maximum operating temperature | 100 °C |
Minimum operating temperature | -40 °C |
organize | 7 DEDICATED INPUTS, 211 I/O |
Output function | MACROCELL |
Package body material | PLASTIC/EPOXY |
encapsulated code | LFBGA |
Encapsulate equivalent code | BGA256,16X16,32 |
Package shape | SQUARE |
Package form | GRID ARRAY, LOW PROFILE, FINE PITCH |
Peak Reflow Temperature (Celsius) | 240 |
power supply | 1.2 V |
Programmable logic type | FLASH PLD |
propagation delay | 5.1 ns |
Certification status | Not Qualified |
Maximum seat height | 1.7 mm |
Maximum supply voltage | 1.26 V |
Minimum supply voltage | 1.14 V |
Nominal supply voltage | 1.2 V |
surface mount | YES |
technology | CMOS |
Temperature level | INDUSTRIAL |
Terminal surface | Tin/Lead (Sn/Pb) |
Terminal form | BALL |
Terminal pitch | 0.8 mm |
Terminal location | BOTTOM |
Maximum time at peak reflow temperature | 30 |
width | 14 mm |