PI6C557-10
Network Clock Generator
Product Features
• 100MHz Differential Output, 33MHz LVCMOS
• Supply voltage of 3.3V ±5%
• 25MHz input frequency
• Jitter 60ps cycle-to-cycle (typ) 100MHz
• Industrial temperature range
• Packaging: (Pb-free and Green)
—16-pin, 173 mils wide TSSOP
The PI6C557-10 is available in a 16 lead 4.4 x 5.0mm TSSOP
package and is operated from a single 3.3V supply. Separate supply
pins are provided for analog core, 100MHz differential output,
and 33MHz LVCMOS output to adhere to lowest risk, best known
power supply partitioning practices.
Description
The PI6C557-10 is an integrated 100MHz differential and 33MHz
LVCMOS clock generator. It uses a 25MHz quartz crystal to provide
an input frequency reference. The high performance internal PLL
multiplier is a proven design that ships world-wide for PCI Express
applications.
Block Diagram
VDD
5
100M
100M
Phase Lock Loop
X1/CLK
25 MHz
crystal or clock X2
Load
Capacitors
Crystal
Driver
33M
5
GND
OE
Pin Configuration
GNDA
VDDA
VDDX
XIN
XOUT
GNDX
GND
VDD
09-0015
1
2
3
4
5
6
7
8
1
16
15
14
13
12
11
10
9
OE
GND
100M
100M
VDD
VDD33
33M
GND33
PS8982A
07/27/09
PI6C557-10
Network Clock Generator
Pin Description
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Pin Name
GNDA
VDDA
VDDX
XIN
XOUT
GNDX
GND
VDD
GND33
33M
VDD33
VDD
100M
100M
GND
OE
I/O Type
Power
Power
Power
Input
Output
Power
Description
Analog Ground
Analog power, connect to clean 3.3V source
Crystal oscillator circuit power
Crystal input.
Crystal output.
Crystal power ground.
Ground.
Power.
Ground for 33MHz output.
33.3MHz LVCMOS output.
Power for 33MHz output
Power.
Complimentary 100MHz differential output.
100MHz differential output.
Ground.
Output enable, tristates both 100MHz and 33MHz outputs when HIGH. Internal pull-down
is 30Kohm.
Power
Output
Power
Power
Output
Output
Power
Input
Application Information
Decoupling Capacitors
Decoupling capacitors of 0.01μF should be connected between
each V
DD
pin and the ground plane and placed as close to the
V
DD
pin as possible.
09-0015
2
PS8982A
07/27/09
PI6C557-10
Network Clock Generator
Electrical Specifications
Maximum Ratings
Supply Voltage to Ground Potential......................................................... 5.5V
All Inputs and Outputs ..................................................... -0.5V to V
DD
+0.5V
Ambient Operating Temperature ................................................-40 to +85
°
C
Storage Temperature .................................................................-65 to +150
°
C
Junction Temperature ........................................................................... 150
°
C
Soldering Temperature ......................................................................... 260
°
C
Note:
Stresses greater than those listed under MAXIMUM RAT-
INGS may cause permanent damage to the device. This is
a stress rating only and functional operation of the device
at these or any other conditions above those indicated in
the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for ex-
tended periods may affect reliability.
DC Characteristics
(V
DD
= 3.3V ± 5%, T
A
= -40°C to +85°C)
Symbol
V
DD
V
IH
V
IL
I
IL
I
DD
I
DDOE
C
IN
C
OUT
L
PIN
Parameter
Supply Voltage
Input High Voltage
(1)
Input Low Voltage
(1)
Input Leakage Current
Conditions
OE
OE
0 < Vin < V
DD
Min.
3.135
2.0
GND -0.3
-20
Typ.
3.3
Max.
3.465
V
DD
+0.3
0.8
150
51
40
Unit
V
V
V
μA
mA
mA
pF
pF
nH
With input pull-up and
pull-downs
Operating Supply Current Normal Operation
OE = HIGH
Input Capacitance
Input pin capacitance
Output Capacitance
Output pin capacitance
Pin Inductance
35
27
5
6.5
5
Notes:
1. Single edge is monotonic when transitioning through region.
09-0015
3
PS8982A
07/27/09
PI6C557-10
Network Clock Generator
100MHz Differential DC Characteristics
(V
DD
= 3.3V ± 5%, TA = -40
°
C to +85
°
C)
to 3.465V unless otherwise stated below.)
Symbol
V
OD
V
OC
Parameter
Differential Output Voltage
Common Mode Voltage
Conditions
Min.
400
1.0
Typ.
725
1.25
Max.
850
1.6
Units
mV
V
100MHz Differential AC Characteristics
(V
DD
= 3.3V ± 5%, TA = -40
°
C to +85
°
C)
t465V)
Symbol
f
out
t
r
/t
f
t
DC
Parameter
Output Frequency
Output Rise/Fall time
Output duty cycle
Phase Jitter
1E-6 BER
PCIE Gen 1 (pk-pk)
20% - 80% 100-Ohm
Differential Termination
C
L
= 10pF
47
53
86
%
ps
1
1.2
Conditions
Min.
Typ.
Max.
100
1.4
Units
MHz
ns
33MHz LVCMOS DC Characteristics
(V
DD
= 3.3V ± 5%, TA = -40
°
C to +85
°
C)
t 3.465V unless otherwise stated below.)
Symbol
V
OL
V
OH
Z
O
Parameter
Output Voltage Low
Output Voltage High
Output Impedance
Conditions
V
DD
= 3.135V, I
OL
= 6mA
V
DD
= 3.135V, I
OH
= –6mA
2.4
45
Min.
Typ.
Max.
0.4
Units
V
Ω
33MHz LVCMOS AC Characteristics
(V
DD
= 3.3V ± 5%, TA = -40
°
C to +85
°
C)
tV to 3.465V)
Symbol
f
out
t
r
/t
f
t
DC
J
CC
Parameter
Output Frequency
Output Rise/Fall time
Output Duty Cycle
Jitter, Cycle-to-Cycle
20% to 80%, C
L
= 10pF
t
DC
= t
H
/t
CY
, t
H
= High Pulse Width,
t
CY
= Output Cycle Time, @ V
DD
/2
45
3
Conditions
Min.
Typ.
Max.
33.3
4
55
300
Units
MHz
ns
%
ps
Notes:
1. Measured from the V
DD
/2 of the input to the differential output crossing point
2. Defined as skew between outputs at the same supply voltage and with equal load condition. Measured at the outputs differential crossing point.
3. Defined as skew between outputs on different parts operating at the same supply voltage and with equal load condition. Measured at the
outputs differential crossing point.
4. All parameters are measured at 500MHz unless noted otherwise
09-0015
4
PS8982A
07/27/09
PI6C557-10
Network Clock Generator
Thermal Characteristics
Symbol
θ
JA
θ
JC
Parameter
Thermal Resistance Junction to Ambient
Thermal Resistance Junction to Case
Conditions
Still air
Min.
Typ.
Max.
90
24
Unit
°
C/W
°
C/W
Recomended Crystal Specification
Pericom recommends SRX7278 for optimium performance.
Parameter
Mode of Oscillation
Frequency
Frequency Tolerance
Temperature and Aging Stability
Load Cap
Equivelent Series Resistance
Drive Level
Value
Fundamental AT
25
±20
±30
20
35
100
Units
MHz
PPM
pF
Ω
μW
3.3V Differential Driver Termination
3.3V
3.3V
Driver
50Ω
R1
100Ω
50Ω
100Ω Differential Transmission Line
A general interface is shown above. In a 100 differential transmission line environment, drivers require a
matched load termination of 100 across near the receiver input.
09-0015
5
PS8982A
07/27/09
京公网安备 11010802033920号
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