time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are
advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. B
07/10/06
1
IS45S32400B
DEVICE OVERVIEW
The 128Mb SDRAM is a high speed CMOS, dynamic
random-access memory designed to operate in 3.3V V
DD
and 3.3V V
DDQ
memory systems containing 134,217,728
bits. Internally configured as a quad-bank DRAM with a
synchronous interface. Each 33,554,432-bit bank is orga-
nized as 4,096 rows by 256 columns by 32 bits.
The 128Mb SDRAM includes an AUTO REFRESH MODE,
and a power-saving, power-down mode. All signals are
registered on the positive edge of the clock signal, CLK. All
inputs and outputs are LVTTL compatible.
The 128Mb SDRAM has the ability to synchronously burst
data at a high data rate with automatic column-address
generation, the ability to interleave between internal banks
to hide precharge time and the capability to randomly
change column addresses on each clock cycle during
burst access.
ISSI
®
A self-timed row precharge initiated at the end of the burst
sequence is available with the AUTO PRECHARGE func-
tion enabled. Precharge one bank while accessing one of the
other three banks will hide the precharge cycles and provide
seamless, high-speed, random-access operation.
SDRAM read and write accesses are burst oriented starting at
a selected location and continuing for a programmed num-
ber of locations in a programmed sequence. The registra-
tion of an ACTIVE command begins accesses, followed by
a READ or WRITE command. The ACTIVE command in
conjunction with address bits registered are used to select
the bank and row to be accessed (BA0, BA1 select the
bank; A0-A11 select the row). The READ or WRITE
commands in conjunction with address bits registered are
used to select the starting column location for the burst
access.
Programmable READ or WRITE burst lengths consist of 1,
2, 4 and 8 locations or full page, with a burst terminate
option.
FUNCTIONAL BLOCK DIAGRAM (FOR 1MX32X4 BANKS)
CLK
CKE
CS
RAS
CAS
WE
DQM0 - DQM3
COMMAND
DECODER
&
CLOCK
GENERATOR
DATA IN
BUFFER
32
32
4
MODE
REGISTER
12
REFRESH
CONTROLLER
DQ 0-31
SELF
REFRESH
CONTROLLER
A10
A11
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
BA0
BA1
12
DATA OUT
BUFFER
32
32
V
DD
/V
DDQ
V
ss
/V
ss
Q
REFRESH
COUNTER
4096
4096
4096
4096
ROW DECODER
MULTIPLEXER
MEMORY CELL
ARRAY
12
ROW
ADDRESS
LATCH
12
ROW
ADDRESS
BUFFER
BANK 0
SENSE AMP I/O GATE
COLUMN
ADDRESS LATCH
8
256
(x 32)
BANK CONTROL LOGIC
BURST COUNTER
COLUMN DECODER
COLUMN
ADDRESS BUFFER
8
2
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. B
07/10/06
IS45S32400B
PIN CONFIGURATIONS
86 pin TSOP - Type II for x32
V
DD
DQ0
V
DD
Q
DQ1
DQ2
V
SS
Q
DQ3
DQ4
V
DD
Q
DQ5
DQ6
V
SS
Q
DQ7
NC
V
DD
DQM0
WE
CAS
RAS
CS
A11
BA0
BA1
A10
A0
A1
A2
DQM2
V
DD
NC
DQ16
V
SS
Q
DQ17
DQ18
V
DD
Q
DQ19
DQ20
V
SS
Q
DQ21
DQ22
V
DD
Q
DQ23
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
V
SS
DQ15
V
SS
Q
DQ14
DQ13
V
DD
Q
DQ12
DQ11
V
SS
Q
DQ10
DQ9
V
DD
Q
DQ8
NC
V
SS
DQM1
NC
NC
CLK
CKE
A9
A8
A7
A6
A5
A4
A3
DQM3
V
SS
NC
DQ31
V
DD
Q
DQ30
DQ29
V
SS
Q
DQ28
DQ27
V
DD
Q
DQ26
DQ25
V
SS
Q
DQ24
V
SS
ISSI
®
PIN DESCRIPTIONS
A0-A11
A0-A7
BA0, BA1
DQ0 to DQ31
CLK
CKE
CS
RAS
CAS
Row Address Input
Column Address Input
Bank Select Address
Data I/O
System Clock Input
Clock Enable
Chip Select
Row Address Strobe Command
Column Address Strobe Command
WE
DQM0-DQM3
V
DD
Vss
V
DDQ
Vss
Q
NC
Write Enable
x32 Input/Output Mask
Power
Ground
Power Supply for I/O Pin
Ground for I/O Pin
No Connection
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. B
07/10/06
3
IS45S32400B
PIN CONFIGURATION
ISSI
1 2 3 4 5 6 7 8 9
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
®
PACKAGE CODE: B 90 BALL FBGA (Top View) (8.00 mm x 13.00 mm Body, 0.8 mm Ball Pitch)
DQ26 DQ24
VSS
VDD DQ23 DQ21
VDDQ VSSQ DQ19
DQ22 DQ20 VDDQ
DQ17 DQ18 VDDQ
NC
A2
A10
NC
BA0
CAS
VDD
DQ6
DQ1
DQ16 VSSQ
DQM2 VDD
A0
BA1
CS
A1
A11
RAS
DQ28 VDDQ VSSQ
VSSQ DQ27 DQ25
VSSQ DQ29 DQ30
VDDQ DQ31
VSS DQM3
A4
A7
CLK
DQM1
A5
A8
CKE
NC
NC
A3
A6
NC
A9
NC
VSS
WE
DQM0
DQ7 VSSQ
DQ5 VDDQ
DQ3 VDDQ
VDDQ DQ8
VSSQ DQ10 DQ9
VSSQ DQ12 DQ14
DQ11 VDDQ VSSQ
DQ13 DQ15
VSS
VDDQ VSSQ DQ4
VDD
DQ0
DQ2
PIN DESCRIPTIONS
A0-A11
A0-A7
BA0, BA1
DQ0 to DQ31
CLK
CKE
CS
RAS
CAS
Row Address Input
Column Address Input
Bank Select Address
Data I/O
System Clock Input
Clock Enable
Chip Select
Row Address Strobe Command
Column Address Strobe Command
WE
DQM0-DQM3
V
DD
Vss
V
DDQ
Vss
Q
NC
Write Enable
x32 Input/Output Mask
Power
Ground
Power Supply for I/O Pin
Ground for I/O Pin
No Connection
4
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. B
07/10/06
IS45S32400B
PIN FUNCTIONS
Symbol
A0-A11
Type
Input Pin
Function (In Detail)
Address Inputs: A0-A11 are sampled during the ACTIVE
ISSI
®
command (row-address A0-A11) and READ/WRITE command (column address A0-
A7), with A10 defining auto precharge) to select one location out of the memory array in
the respective bank. A10 is sampled during a PRECHARGE command to determine if
all banks are to be precharged (A10 HIGH) or bank selected by
BA0, BA1 (LOW). The address inputs also provide the op-code during a LOAD MODE
REGISTER command.
BA0, BA1
CAS
CKE
Input Pin
Input Pin
Input Pin
Bank Select Address: BA0 and BA1 defines which bank the ACTIVE, READ, WRITE or
PRECHARGE command is being applied.
CAS,
in conjunction with the
RAS
and
WE,
forms the device command. See the
"Command Truth Table" for details on device commands.
The CKE input determines whether the CLK input is enabled. The next rising edge of the
CLK signal will be valid when is CKE HIGH and invalid when LOW. When CKE is LOW,
the device will be in either power-down mode, clock suspend mode, or self refresh
mode. CKE is an asynchronous input.
CLK is the master clock input for this device. Except for CKE, all inputs to this device
are acquired in synchronization with the rising edge of this pin.
The
CS
input determines whether command input is enabled within the device.
Command input is enabled when
CS
is LOW, and disabled with
CS
is HIGH. The device
remains in the previous state when
CS
is HIGH.
DQM0 - DQM3 control the four bytes of the I/O buffers (DQ0-DQ31). In read
mode, DQMn control the output buffer. When DQMn is LOW, the corresponding buffer
byte is enabled, and when HIGH, disabled. The outputs go to the HIGH impedance
state whenDQMn is HIGH. This function corresponds to
OE
in conventional DRAMs. In
write mode, DQMn control the input buffer. When DQMn is LOW, the corresponding
buffer byte is enabled, and data can be written to the device. When DQMn is HIGH,
input data is masked and cannot be written to the device.
Data on the Data Bus is latched on these pins during Write commands, and buffered
after Read commands.
RAS,
in conjunction with
CAS
and
WE,
forms the device command. See the "Command
Truth Table" item for details on device commands.
WE,
in conjunction with
RAS
and
CAS,
forms the device command. See the "Command
Truth Table" item for details on device commands.
V
DDQ
is the output buffer power supply.
V
DD
is the device internal power supply.
V
SSQ
is the output buffer ground.
V
SS
is the device internal ground.
CLK
CS
Input Pin
Input Pin
DQM0-DQM3
Input Pin
DQ0-DQ31
RAS
WE
V
DDQ
V
DD
V
SSQ
V
SS
Input/Output Pin
Input Pin
Input Pin
Power Supply Pin
Power Supply Pin
Power Supply Pin
Power Supply Pin
Integrated Silicon Solution, Inc. — www.issi.com —
This book is based on OrCAD and Allegro in the currently stable SPB 16.6 version of Cadence, and introduces in detail the methods and techniques of using SPB 16.6 to implement schematics and high-spee...
When you need to transplant the algorithm you have written to the DSP development board and run it well, what work needs to be done? The following is divided into two parts. The first part is transpla...
I wrote a program for a matrix keyboard, but it doesn't work very well.Schematic diagram:Code:
//Initialize PA8 and PD2 as output ports and enable the clocks of these two ports//LED IO initialization
...
TE Connectivity (TE) Webinar Learning Center has carefully prepared a wealth of technical lectures and video training for you. It not only restores the TE booth at the large exhibition site, but also ...
The CH224 is so easy to use (this is really worth praising). After doing the initial test, I felt that there was nothing to test, so I started to draw the circuit directly. This time I plan to use the...
1. Introduction
Intelligent mobile robots are a type of robot system that can sense the environment and its own state through sensors
,
achieve autonomous movemen...[Details]
introduction
In recent years, with the increasing maturity of LED technology, LED light sources have been increasingly widely used due to their advantages of using low-voltage power supply, low...[Details]
Digital blogger @B·WONG released a set of photos today and claimed that the photos were real photos of Huawei Mate 40 Pro, but the blogger deleted them in the evening. In addition, digital blogger ...[Details]
According to the latest patent application published by the China National Intellectual Property Administration, Zhuhai Meizu Technology Co., Ltd. has applied for a utility model patent, which...[Details]
introduction Improving the energy structure, increasing energy efficiency, and taking the path of low-carbon economic development have become the inevitable choice to solve the problems of energy...[Details]
Stack growth and big-endian/little-endian issues are two issues related to the CPU. 1. Let's first look at the problem of the stack (STACK). The local variables of a function are all stored in the ...[Details]
Microchip Launches New VelocityDRIVE™ Software Platform and Automotive-Grade Multi-Gigabit Ethernet Switch to Support Software-Defined Cars
VelocityDRIVE software platform implements...[Details]
1 Introduction
In real life, humidity measurement and control are widely used in the fields of textile industry, forestry, chemical industry and meteorological observation. Traditional manual testing...[Details]
Huawei supply chain and wafer test card manufacturer China Precision Testing announced today (3) that its August revenue was NT$367 million (same unit below), a 7.4% increase from the previous month ...[Details]
The SM-T54 is a USB-C docking station. You can connect a computer with USB 3.1 protocol to a monitor, TV or other display device with HDMI or VGA through this product. The product can connect to HD...[Details]
What will be the key driving force behind this new mobility revolution in the coming decades? Recently, CEOs of several well-known established car companies have all talked about the topic of future ...[Details]
MediaTek releases Dimensity 8300 mobile chip, comprehensive innovation to promote end-side generative AI innovation November 21, 2023 – MediaTek released the Dimensity 8300 5G generative AI mobile...[Details]
Recently, the Qinghai Provincial Science and Technology Department organized relevant experts to evaluate the results of the "Solar Grade 125×125 Monocrystalline Silicon Wafer Cutting Technology Re...[Details]
In our previous blog notes, we have explained how improving the efficiency of electric vehicle powertrains can increase their range (Note I) and how better software controlling inverters and electr...[Details]
DIY/Open Source Hardware
京公网安备 11010802033920号
EEWORLD
