E28F128J3A-115 datasheet, PDF - EEWORLD Datasheet

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E28F128J3A-115: Description4M X 16 FLASH 2.7V PROM, 120 ns, PBGA64; Categorystorage; File Size534KB，72 Pages; ManufacturerIntel; Websitehttp://www.intel.com/

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E28F128J3A-115 Overview

4M X 16 FLASH 2.7V PROM, 120 ns, PBGA64

E28F128J3A-115 Parametric

Parameter Name	Attribute value
Number of functions	1
Number of terminals	64
Maximum operating temperature	85 Cel
Minimum operating temperature	-40 Cel
Maximum supply/operating voltage	3.6 V
Minimum supply/operating voltage	2.7 V
Rated supply voltage	3 V
maximum access time	120 ns
Processing package description	BGA-64
state	ACTIVE
packaging shape	RECTANGULAR
Package Size	GRID ARRAY, THIN PROFILE
surface mount	Yes
Terminal form	BALL
Terminal spacing	1 mm
terminal coating	NOT SPECIFIED
Terminal location	BOTTOM
Packaging Materials	PLASTIC/EPOXY
Temperature level	INDUSTRIAL
memory width	16
organize	4M X 16
storage density	6.71E7 deg
operating mode	ASYNCHRONOUS
Number of digits	4.19E6 words
Number of digits	4M
Spare memory width	8
Memory IC type	FLASH 2.7V PROM
serial parallel	PARALLEL

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Intel StrataFlash

Memory (J3)

256-Mbit (x8/x16)

Datasheet

Product Features

■

Performance

— 110/115/120/150 ns Initial Access Speed

— 125 ns Initial Access Speed (256 Mbit

density only)

— 25 ns Asynchronous Page mode Reads

— 30 ns Asynchronous Page mode Reads

(256Mbit density only)

— 32-Byte Write Buffer

—6.8 µs per byte effective

programming time

Software

— Program and Erase suspend support

— Flash Data Integrator (FDI), Common

Flash Interface (CFI) Compatible

Security

— 128-bit Protection Register

—64-bit Unique Device Identifier

—64-bit User Programmable OTP Cells

— Absolute Protection with V

PEN

= GND

— Individual Block Locking

— Block Erase/Program Lockout during

Power Transitions

■

Architecture

— Multi-Level Cell Technology: High

Density at Low Cost

— High-Density Symmetrical 128-Kbyte

Blocks

—256 Mbit (256 Blocks) (0.18µm only)

—128 Mbit (128 Blocks)

—64 Mbit (64 Blocks)

—32 Mbit (32 Blocks)

Quality and Reliability

— Operating Temperature:

-40 °C to +85 °C

— 100K Minimum Erase Cycles per Block

— 0.18 µm ETOX™ VII Process (J3C)

— 0.25 µm ETOX™ VI Process (J3A)

Packaging and Voltage

— 56-Lead TSOP Package

— 64-Ball Intel

Easy BGA Package

— Lead-free packages available

— 48-Ball Intel

VF BGA Package (32 and

64 Mbit) (x16 only)

— V

2.7 V to 3.6 V

— V

CCQ

= 2.7 V to 3.6 V

Capitalizing on Intel’s 0.25 and 0.18 micron, two-bit-per-cell technology, the Intel StrataFlash

Memory (J3)

device provides 2X the bits in 1X the space, with new features for mainstream performance. Offered in 256-

Mbit (32-Mbyte), 128-Mbit (16-Mbyte), 64-Mbit, and 32-Mbit densities, the J3 device brings reliable, two-bit-

per-cell storage technology to the flash market segment. Benefits include more density in less space, high-speed

interface, lowest cost-per-bit NOR device, support for code and data storage, and easy migration to future

devices.

Using the same NOR-based ETOX™ technology as Intel’s one-bit-per-cell products, the J3 device takes

advantage of over one billion units of flash manufacturing experience since 1987. As a result, J3 components

are ideal for code and data applications where high density and low cost are required. Examples include

networking, telecommunications, digital set top boxes, audio recording, and digital imaging.

By applying FlashFile™ memory family pinouts, J3 memory components allow easy design migrations from

existing Word-Wide FlashFile memory (28F160S3 and 28F320S3), and first generation Intel StrataFlash

memory (28F640J5 and 28F320J5) devices.

J3 memory components deliver a new generation of forward-compatible software support. By using the

Common Flash Interface (CFI) and the Scalable Command Set (SCS), customers can take advantage of density

upgrades and optimized write capabilities of future Intel StrataFlash

memory devices. Manufactured on Intel

0.18 micron ETOX™ VII (J3C) and 0.25 micron ETOX™ VI (J3A) process technology, the J3 memory device

provides the highest levels of quality and reliability.

Notice:

This document contains information on new products in production. The specifications are

subject to change without notice. Verify with your local Intel sales office that you have the latest

datasheet before finalizing a design.

Order Number: 290667-021

March 2005

Contents

1.0

Introduction....................................................................................................................................7

1.1

1.2

2.0

2.1

2.2

3.0

3.1

3.2

3.3

4.0

4.1

4.2

4.3

4.4

5.0

5.1

5.2

6.0

6.1

6.2

7.0

7.1

7.2

7.3

7.4

7.5

7.6

8.0

8.1

8.2

8.3

9.0

9.1

Nomenclature .......................................................................................................................7

Conventions..........................................................................................................................7

Block Diagram ......................................................................................................................9

Memory Map .......................................................................................................................10

56-Lead TSOP Package .....................................................................................................11

Easy BGA (J3) Package .....................................................................................................12

VF-BGA (J3) Package ........................................................................................................13

Easy BGA Ballout (32/64/128/256 Mbit) .............................................................................14

56-Lead TSOP (32/64/128/256 Mbit)..................................................................................15

VF BGA Ballout (32 and 64 Mbit) .......................................................................................15

Signal Descriptions .............................................................................................................16

Absolute Maximum Ratings ................................................................................................18

Operating Conditions ..........................................................................................................18

DC Current Characteristics .................................................................................................19

DC Voltage Characteristics.................................................................................................20

Read Operations.................................................................................................................22

Write Operations .................................................................................................................26

Block Erase, Program, and Lock-Bit Configuration Performance .......................................27

Reset Operation..................................................................................................................29

AC Test Conditions.............................................................................................................29

Capacitance ........................................................................................................................30

Power-Up/Down Characteristics.........................................................................................31

Power Supply Decoupling...................................................................................................31

Reset Characteristics..........................................................................................................31

Bus Operations Overview ...................................................................................................32

9.1.1 Bus Read Operation ..............................................................................................33

9.1.2 Bus Write Operation ..............................................................................................33

9.1.3 Output Disable .......................................................................................................33

9.1.4 Standby..................................................................................................................34

9.1.5 Reset/Power-Down ................................................................................................34

Functional Overview

.....................................................................................................................8

Package Information

...................................................................................................................11

Ballout and Signal Descriptions

................................................................................................14

Maximum Ratings and Operating Conditions...........................................................................18

Electrical Specifications

.............................................................................................................19

AC Characteristics

......................................................................................................................22

Power and Reset Specifications

................................................................................................31

Bus Operations

............................................................................................................................32

Datasheet

Contents

9.2

Device Commands ............................................................................................................. 35

10.0 Read Operations..........................................................................................................................

10.1

Read Array.......................................................................................................................... 37

10.1.1 Asynchronous Page Mode Read ........................................................................... 37

10.1.2 Enhanced Configuration Register (ECR)............................................................... 38

Read Identifier Codes ......................................................................................................... 39

10.2.1 Read Status Register............................................................................................. 39

Read Query/CFI.................................................................................................................. 41

Byte/Word Program ............................................................................................................ 42

Write to Buffer..................................................................................................................... 42

Program Suspend............................................................................................................... 43

Program Resume................................................................................................................ 43

Block Erase......................................................................................................................... 44

Block Erase Suspend ......................................................................................................... 44

Erase Resume .................................................................................................................... 45

Set Block Lock-Bit............................................................................................................... 46

Clear Block Lock-Bits.......................................................................................................... 46

Protection Register Program .............................................................................................. 47

13.3.1 Reading the Protection Register............................................................................ 47

13.3.2 Programming the Protection Register.................................................................... 47

13.3.3 Locking the Protection Register............................................................................. 47

Array Protection .................................................................................................................. 49

Set Read Configuration Register Command ...................................................................... 50

Status (STS) ....................................................................................................................... 50

10.2

10.3

11.1

11.2

11.3

11.4

12.1

12.2

12.3

13.1

13.2

13.3

11.0 Programming Operations

........................................................................................................... 42

12.0 Erase Operations.........................................................................................................................

13.0 Security Modes

............................................................................................................................ 46

13.4

14.1

14.2

14.0 Special Modes..............................................................................................................................

Appendix A Common Flash Interface.................................................................................................52

Appendix B Flow Charts

......................................................................................................................59

Appendix C Design Considerations

...................................................................................................68

Appendix D Additional Information

....................................................................................................70

Appendix E Ordering Information.......................................................................................................71

Datasheet

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