Low Skew 1 to 2 Clock Buffer
74FCT38072S
DATASHEET
Description
The 74FCT38072S is a low skew, single input to two output,
clock buffer. The 74FCT38072S has best in class additive
phase Jitter of sub 50 fsec.
IDT makes many non-PLL and PLL based low skew output
devices as well as Zero Delay Buffers to synchronize clocks.
Contact us for all of your clocking needs.
Features
•
•
•
•
•
•
•
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Low additive phase jitter RMS: 50fs
Extremely low skew outputs (50ps)
Low cost clock buffer
Packaged in 8-pin SOIC and 8-pin DFN, Pb-free
Input/Output clock frequency up to 200 MHz
Low power CMOS technology
Operating voltages of 1.8V to 3.3V
Extended temperature range (-40° to +105°C)
Block Diagram
Q0
ICLK
Q1
74FCT38072S REVISION A 03/18/15
1
©2015 Integrated Device Technology, Inc.
74FCT38072S DATASHEET
Pin Assignments
VDD
VDD
ICLK
GND
1
2
3
4
8-pin SOIC
8
7
6
5
GND
Q1
Q0
GND
VDD
VDD
ICLK
GND
1
2
3
4
8
7
6
5
GND
Q1
Q0
GND
8-pin DFN
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
Pin
Name
VDD
VDD
ICLK
GND
GND
Q0
Q1
GND
Pin
Type
Power
Power
Input
Power
Power
Output
Output
Power
Connect to +1.8V, +2.5 V, or +3.3 V.
Connect to +1.8V, +2.5 V, or +3.3 V.
Clock input.
Connect to ground.
Connect to ground.
Clock output 0.
Clock output 1.
Connect to ground.
Pin Description
External Components
A minimum number of external components are required for proper operation. A decoupling capacitor of 0.01 µF should be
connected between VDD pin and GND pin, as close to the device as possible. A 33
series terminating resistor may be used
on each clock output if the trace is longer than 1 inch.
To achieve the low output skew that the 74FCT38072S is capable of, careful attention must be paid to board layout. Essentially,
both outputs must have identical terminations, identical loads and identical trace geometries. If they do not, the output skew will
be degraded. For example, using a 30
series termination on one output (with 33
on the others) will cause at least 15 ps of
skew.
LOW SKEW 1 TO 2 CLOCK BUFFER
2
REVISION A 03/18/15
74FCT38072S DATASHEET
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the 74FCT38072S. These ratings, which are standard
values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other
conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the
recommended operating temperature range.
Item
Supply Voltage, VDD
Outputs
ICLK
Ambient Operating Temperature (extended)
Storage Temperature
Junction Temperature
Soldering Temperature
3.465V
-0.5 V to VDD+0.5 V
3.465V
-40 to +105C
-65 to +150C
125C
260C
Rating
Recommended Operation Conditions
Parameter
Ambient Operating Temperature (extended)
Power Supply Voltage (measured in respect to GND)
Min.
-40
+1.71
Typ.
Max.
+105
+3.465
Units
C
V
REVISION A 03/18/15
3
LOW SKEW 1 TO 2 CLOCK BUFFER
74FCT38072S DATASHEET
DC Electrical Characteristics
(VDD = 1.8V, 2.5V, 3.3V)
VDD=1.8V ±5%
, Ambient temperature -40° to +105°C, unless stated otherwise
Parameter
Operating Voltage
Input High Voltage, ICLK
Input Low Voltage, ICLK
Output High Voltage
Output Low Voltage
Operating Supply Current
Nominal Output Impedance
Input Capacitance
Notes: 1. Nominal switching threshold is VDD/2
Symbol
VDD
V
IH
V
IL
V
OH
V
OL
IDD
Z
O
C
IN
ICLK
Note 1
Note 1
Conditions
Min.
1.71
0.7xVDD
1.3
Typ.
Max.
1.89
VDD
0.3xVDD
0.35
Units
V
V
V
V
V
mA
pF
I
OH
= -10 mA
I
OL
= 10mA
No load, 135 MHz
15
17
5
VDD=2.5 V ±5%
, Ambient temperature -40° to +105°C, unless stated otherwise
Parameter
Operating Voltage
Input High Voltage, ICLK
Input Low Voltage, ICLK
Output High Voltage
Output Low Voltage
Operating Supply Current
Nominal Output Impedance
Input Capacitance
Symbol
VDD
V
IH
V
IL
V
OH
V
OL
IDD
Z
O
C
IN
ICLK
Note 1
Note 1
Conditions
Min.
2.375
0.7xVDD
1.8
Typ.
Max.
2.625
VDD
0.3xVDD
0.5
Units
V
V
V
V
V
mA
pF
I
OH
= -16 mA
I
OL
= 16 mA
No load, 135 MHz
18
17
5
VDD=3.3 V ±5%
, Ambient temperature -40° to +105°C, unless stated otherwise
Parameter
Operating Voltage
Input High Voltage, ICLK
Input Low Voltage, ICLK
Output High Voltage
Output Low Voltage
Operating Supply Current
Nominal Output Impedance
Input Capacitance
Symbol
VDD
V
IH
V
IL
V
OH
V
OL
IDD
Z
O
C
IN
ICLK
Note 1
Note 1
Conditions
Min.
3.15
0.7xVDD
2.2
Typ.
Max.
3.45
VDD
0.3xVDD
0.7
Units
V
V
V
V
V
mA
pF
I
OH
= -25 mA
I
OL
= 25 mA
No load, 135 MHz
22
17
5
LOW SKEW 1 TO 2 CLOCK BUFFER
4
REVISION A 03/18/15
74FCT38072S DATASHEET
AC Electrical Characteristics
(VDD = 1.8V, 2.5V, 3.3V)
VDD = 1.8V ±5%
, Ambient Temperature -40° to +105°C, unless stated otherwise
Parameter
Input Frequency
Output Rise Time
Output Fall Time
Start-up Time
Propagation Delay
Buffer Additive Phase Jitter, RMS
Output to Output Skew
Device to Device Skew
t
OR
t
OF
t
START-UP
0.36 to 1.44 V, C
L
=5 pF
1.44 to 0.36 V, C
L
=5 pF
Part start-up time for valid outputs
after VDD ramp-up
Note 1
125MHz, Integration Range:
12kHz-20MHz
Rising edges at VDD/2, Note 2
Rising edges at VDD/2
50
1.5
2.5
Symbol
Conditions
Min.
0
Typ.
0.6
0.6
Max.
200
1.0
1.0
2
4
0.05
65
200
Units
MHz
ns
ns
ms
ns
ps
ps
ps
VDD = 2.5 V ±5%
, Ambient Temperature -40° to +105°C, unless stated otherwise
Parameter
Input Frequency
Output Rise Time
Output Fall Time
Start-up Time
Propagation Delay
Buffer Additive Phase Jitter, RMS
Output to Output Skew
Device to Device Skew
t
OR
t
OF
t
START-UP
0.5 to 2.0 V, C
L
=5 pF
2.0 to 0.5 V, C
L
=5 pF
Part start-up time for valid outputs
after VDD ramp-up
Note 1
125MHz, Integration Range:
12kHz-20MHz
Rising edges at VDD/2, Note 2
Rising edges at VDD/2
50
1.8
2.5
Symbol
Conditions
Min.
0
Typ.
0.6
0.6
Max.
200
1.0
1.0
2
4.5
0.05
65
200
Units
MHz
ns
ns
ms
ns
ps
ps
ps
VDD = 3.3 V ±5%
, Ambient Temperature -40° to +105°C, unless stated otherwise
Parameter
Input Frequency
Output Rise Time
Output Fall Time
Start-up Time
Propagation Delay
Buffer Additive Phase Jitter, RMS
Output to Output Skew
Device to Device Skew
t
OR
t
OF
t
START-UP
0.66 to 2.64 V, C
L
=5 pF
2.64 to 0.66 V, C
L
=5 pF
Part start-up time for valid outputs
after VDD ramp-up
Note 1
125MHz, Integration Range:
12kHz-20MHz
Rising edges at VDD/2, Note 2
Rising edges at VDD/2
50
1.5
2.5
Symbol
Conditions
Min.
0
Typ.
0.6
0.6
Max.
200
1.0
1.0
2
4
0.05
65
200
Units
MHz
ns
ns
ms
ns
ps
ps
ps
Notes:
1. With rail to rail input clock
2. Between any 2 outputs with equal loading.
3. Duty cycle on outputs will match incoming clock duty cycle. Consult IDT for tight duty cycle clock generators.
REVISION A 03/18/15
5
LOW SKEW 1 TO 2 CLOCK BUFFER
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